DFT Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

DFT Engineer 2 Locations Meet the Team We are a leading Design for Test (DFT) group, delivering End-to-End solutions for Cisco's flagship products, including Cisco Silicon One™. Our chips are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation. Your Impact As an Experienced DFT Engineer, you will: • Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification. • Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams. • Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST. • Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality. • Establish, standardize, and evolve DFT methodologies and best practices across projects. Minimum Qualifications • B.Sc. or M.Sc . in Electrical Engineering or a related field. • Strong hands-on experience with MBIST, and a passion for expanding expertise to scan insertion, ATPG, and boundary scan technologies. • Proven experience across the full silicon product lifecycle, from pre-silicon design to silicon bring-up and production. • Strong communication and collaboration

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.