Hardware Engineering Technical Leader

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Hardware Engineering Technical Leader Bangalore, India Meet the Team Cisco Common Hardware Group (CHG) SI team is seeking a Signal and Power Integrity Technical Lead for design and analysis of high-speed interconnects and power distribution networks. As a member of the SI team, you will help develop the next generations of Cisco Switch and Router nad AI/ML products, participate in the definition and design of current and next-generation ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with system architects, ASIC engineers, package engineers, and versatile and knowledgeable SI/PI engineers in the creation of next-generation networking products. Your Impact Model and simulate High-speed links, including high-speed I/O, IC package, and system interconnections. Model and analyze power delivery networks. Electromagnetic modeling of complex 3D structures. Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs. Write signal integrity design guidelines, test plans, and test reports. Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues. Support prototype function bring-up, validation, and troubleshooting. Work closely with other hardware function teams including HW design, eCAD, Mechanical, Power, EMC, and Diagnostics to deliver first-class products. Provide technical leadership and mentorship to junior SI/PI engineers, foster skill development and best practices within the team. Drive definition, implementation, and continuous improvement of advanced SI/PI methodologies, simulation flows, and design processes. Contribute to the overall SI/PI technology roadmap, evaluate new tools, techniques, and design approaches to

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