EMIR/ESD Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

Not verified

Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

EMIR/ESD Engineer Armenia Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact Drive Cisco's silicon innovation by performing comprehensive chip-level EMIR and ESD analysis to ensure the reliability of our next-generation designs. Investigate complex EMIR and ESD results to propose and implement effective optimizations that maintain design integrity. Collaborate with package teams and block owners to guide design fixes and ensure robust power grid performance. Coordinate with EDA tool vendors and flow teams to enhance the accuracy and scalability of our sign-off methodologies. Contribute to the end-to-end physical implementation process to ensure our silicon solutions meet the highest standards for performance and reliability before tape-out. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of hands-on experience in ASIC design and verification. Strong understanding of schematics and layout in FinFET technologies. Experience in deep submicron CMOS technologies. Hands-on experience in RTL-to-GDSII flow, floorplanning, and power planning. Preferred Qualifications Good knowledge of ESD protection concepts and implementation. Familiarity with PnR

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