FewerJobs.
All jobs

ASIC Engineering Technical Leader- STA

Cisco - San Jose, California, US

Posted Jun 8, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified checked Jun 13, 2026
Salary
$211K-$305K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

121% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Jul 9, 2026 From the posting source checked Jun 20, 2026

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineering Technical Leader- STA San Jose, California, US The application window is expected to close on: 07/09/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Your Impact: Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments. What You'll Do: Oversees the definition, architecture and design of high performance ASICs Oversees all applications and code including methodology of reusable code Oversees code creation and determines methodology behind coding Consults for architecture and design decisions for complex areas Drives design solutions across the business Creates guidelines and standards Creates innovative verification strategies Oversees system level verification using test benches Ensures culture of code reviews and postmortems Architects and designs analog/mixed-signal circuits Reviews complex IC designs and makes recommendations for improvements Directs the mixed-signal team to define requirements, influences packaging and hardware team to ensure specifications are met Oversees all physical design functions bringing technical expertise to highly complex scenarios Interfaces with vendors and design leads on complex issues Drives different technology design rules to develop innovative packages Minimum Qualifications: Bachelor's with 10 years of related experience, or Master's with 5 years of related experience, or PhD with

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.

Apply at cisco.wd5.myworkdayjobs.com

Apply link verified; last checked Aug 10, 2026.

What verified means

Verified means a displayed claim has field-level provenance to a source FewerJobs pulled: a government or employer source, or the original job posting. Posting-sourced facts are employer-stated and are labeled separately from government records.

Related jobs