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ASIC Engineering Lead

Cisco - Armenia

Posted May 12, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
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Verification
Not verified checked Jun 13, 2026
Salary
Not verified
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Senior From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Engineering Lead Armenia Meet the Team Join Cisco's CHG Team in Armenia, a team at the forefront of physical design for the globally recognized Silicon One brand. We specialize in chip-level implementation for innovative networking technology, tackling large-scale design challenges with advanced methodologies and best-in-class tools. Our team is a collaborative group of experts dedicated to redefining the boundaries of what is possible in silicon. By driving the physical implementation of high-complexity silicon, we ensure the performance and reliability of the technology that powers tomorrow's connectivity. This is an exciting opportunity to work on cutting-edge networking chips in a dynamic, global environment. Your Impact Lead the end-to-end physical implementation of high-complexity silicon blocks from RTL to tape-out to ensure production-ready design delivery. Apply deep expertise in synthesis, place-and-route, and timing closure to meet stringent performance, power, and area (PPA) goals. Collaborate with global frontend, IP, and CAD teams to resolve complex implementation challenges and ensure seamless system-level integration. Advance physical design methodologies by leading technical investigations and proposing improvements to streamline development flows. Provide technical direction to peers to foster an innovative engineering environment that delivers impactful networking solutions. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. Minimum of 8 years of experience in ASIC design, physical implementation, and verification. Proven expertise in deep submicron CMOS technologies. Extensive knowledge of the full design cycle from RTL to GDSII. Demonstrated mastery in block-level synthesis, place-and-route, and timing closure. Excellent verbal and written communication

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Apply link verified; last checked Aug 3, 2026.

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