ASIC Digital Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

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Childcare support

Not verified

Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Work mode

Hybrid From the posting source checked Jun 20, 2026

In-office days

2 days From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Digital Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team The Common Hardware Group delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. The team designs networking hardware for Enterprises, Service Providers, the Public Sector, and Non-Profit Organizations worldwide. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market, enabling customers to deploy best-of-breed silicon from TOR switches through web-scale data centers and across service provider and enterprise networks with a fully unified routing and switching portfolio. The team is composed of highly skilled engineers working on some of the most complex ASICs in the industry, fostering a collaborative and innovative environment. Joining this team means contributing to groundbreaking solutions that shape the future of networking silicon. Your Impact You will be a key member of the Silicon One development organization, collaborating closely with Front-end RTL and backend physical design teams to deeply understand chip architecture. Drive high-quality Design for Test (DFT) verification to ensure robust and reliable silicon solutions that meet Cisco's standards for performance and innovation. Take part in all aspects of digital design, from micro-architecture to RTL design and qualification. Integrate and verify sub-systems/SoCs, review and enhance RTL codes, and improve flows and methodologies to streamline IP/SoC development and integration. Work closely with the verification team for complex debug and resolution of verification failures, and interact with the physical design team to achieve better physical design

Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a preview and links to the original posting.