ASIC Design Verification Technical Leader - Acacia (hybrid)
Cisco - 2 Locations
Posted May 12, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
- Not verified
- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Market context
- Median wage (BLS OEWS)
- $116,543 national median
- Projected growth (BLS Employment Projections)
- +9.8% - Much faster than average
98% above the BLS national median for software engineering aggregate.
Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
ASIC Design Verification Technical Leader - Acacia (hybrid) 2 Locations The application window is expected to close on: 04/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on June 2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Preferred candidates will be based in Maynard, MA, or Austin, TX and be available to be onsite 3 days per week. Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact The ASIC Design Verification Technical Lead Engineer will be working on next-generation 100G-1.6T coherent optical communications products. This role is for a senior contributor & technical leader focused on verifying highly complex ASICs that are used in these next-generation systems. The role requires someone to demonstrate their experience applying sophisticated verification techniques to ASIC projects:
Read the full description at cisco.wd5.myworkdayjobs.com. FewerJobs shows a source-linked preview and links to the original posting.
Apply link verified; last checked Jun 13, 2026.
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