ASIC Design Engineer - Cisco Silicon One

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Engineer - Cisco Silicon One Tel Aviv-Yafo, Israel Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco's silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what's possible. Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco's future routing portfolio and shaping the Internet for decades to come. Your Impact · Write and review micro-architecture specifications · Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements · Contribute to full chip integration, timing methodology, and analysis · Collaborate with verification engineers to resolve bugs and achieve coverage closure · Work with the physical design team to close timing and PnR issues · Support design methodology evolution and best practices · Perform debug, root-cause analysis, and post-silicon validation in the lab Minimum Qualifications · B.Sc./M.Sc. in Electrical Engineering from a top university · 3+ years of experience in a relevant field · RTL design experience · Familiarity with UVM and functional verification methodologies Preferred Qualifications · Experience with MATLAB simulations and bit-exact modeling environments · Familiarity with mixed-signal systems and environments · Knowledge and hands-on experience with Clock Domain Crossing (CDC) Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly

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