Staff Memory Circuit Design Engineer

Verified benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Verified

No last checked 2026-05-07T13:50:00Z

Salary

$108K-$173K

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

111% above the BLS national median for design aggregate.

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Staff Memory Circuit Design Engineer USA-CA Irvine Alton Parkway Bldg 1 Please Note: 1. If you are a first time user, please create your candidate login account before you apply

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