Senior Firmware Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

$160K-$195K not verified - source not recorded; timestamp not recorded

401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

52% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior Firmware Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Astera Labs is seeking a Senior Firmware Engineer to develop and deliver core firmware for our next-generation connectivity, chiplet, and system products. Firmware is a core differentiator for Astera Labs' products and is treated as a first-class engineering discipline, on par with hardware and silicon design. Key Responsibilities - Architect, develop, and maintain bare-metal and low-level firmware running on embedded microcontrollers within Astera Labs SoCs and systems. - Design and implement device drivers, core firmware services, and hardware abstraction layers for high-speed connectivity products. - Define and implement HW-SW interfaces in close collaboration with RTL, PD, and Architecture teams. - Lead bring-up, debug, and validation of firmware on silicon and system platforms. - Develop and maintain C/C++ firmware codebases, SDKs, and supporting infrastructure. - Build automation, tooling, and diagnostics using Python and scripting frameworks. - Participate in system-level debug involving PCIe, Ethernet, memory subsystems, and interconnect fabrics. -

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