Lead ATE Test Engineer

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About this role

Lead ATE Test Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Lead ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, DDR, NVMe, USB, etc. Basic Qualifications · Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred. · ≥5-year experience releasing complex SoC/silicon products to high volume manufacturing. · Working knowledge of high-speed protocols like PCIe, Ethernet, DDR, NVMe, USB, etc. · Professional attitude with ability to execute on multiple tasks with minimal supervision. · Strong team player with good communication skills to work

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