FPGA Design Engineer (eInfochips an Arrow company)

Verified benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Verified

No last checked 2026-05-07T13:50:00Z

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$66,396 national median

Projected growth (BLS Employment Projections)

+3.5% - Average

Matched to SOC 27-1024 - Design aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

Hires in: TX

About this role

FPGA Design Engineer (eInfochips an Arrow company) US-TX-Texas (Remote Employees)-Mountain Time Zone FPGA Design Engineer (eInfochips an Arrow company) /job/US-TX-Texas-Remote-Employees-Mountain-Time-Zone/FPGA-Design-Engineer--eInfochips-an-Arrow-company-_R242354 US-TX-Texas (Remote Employees)-Mountain Time Zone Posted 30+ Days Ago

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