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Design For Test Engineer (Einfochips Inc)

Arrow Electronics - San Jose, California, United States of America

Posted Apr 24, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified checked Jun 7, 2026
Salary
Not verified
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design For Test Engineer (Einfochips Inc) San Jose, California, United States of America Embrace the role of a Design for Test Engineer and drive innovation in semiconductor design. Leverage your expertise in DFT, pattern simulation, and hardware debugging to support cutting-edge networking solutions. Collaborate with top engineers and work with advanced tools like Mentor Tessent and Synopsys. Shape the future of technology with us!

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Apply link not verified; last-live date unavailable.

What verified means

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