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Design For Test Engineer (Einfochips Inc)

Arrow Financial CORP - US-CA-Mountain View, California (Google)

Posted May 31, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
Not verified
Learning budget
Offered From the posting source checked Jun 20, 2026
Verification
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Salary
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401(k) match
Reported not verified - source not recorded; source URL not recorded; timestamp not recorded

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
Not verified

Company

Company stage
Public-company From the posting source checked Jun 20, 2026
Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
Not verified
Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health

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Apply link verified; last checked Aug 3, 2026.

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