Wireless Design Verification Engineer

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Wireless Design Verification Engineer Irvine, United States of America Join Apple's Wireless Connectivity team developing state-of-the-art WiFi SoCs that power hundreds of millions of Apple products worldwide. You'll be part of our vertically integrated organization shaping next-gen wireless technology from concept through production. As a Senior Wireless Design Verification Engineer, you'll ensure first-time-right silicon success through sophisticated testbenches, comprehensive scenarios, and cutting-edge verification methodologies-enabling multi-gigabit wireless technology connecting the world! As a Senior Wireless Verification Engineer, you will be at the core of our wireless product's success, bridging domains, driving collaborations, and developing verification solutions to ensure excellent products. You will lead verification of controllers, datapaths, subsystems, protocols, low power capabilities, and SOC / integration frameworks. You will leverage and architect environments, develop scenarios, and utilize metrics. You'll develop verification strategies for wireless features enabling advanced applications across Apple's product ecosystem. Lead subsystem-level verification from test planning, environment definition, and design bring-up through feature closure. Architect sophisticated UVM testbench environments, infrastructure frameworks, and reusable verification IP with automation capabilities. Develop constrained random scenarios for complex protocol, and multi-domain behaviors. Lead cross-functional collaboration to define verification requirements, debug complex issues, and drive decisions. Drive coverage-driven methodologies, and metric analysis frameworks. Minimum Qualifications: BS and a minimum of 10 years relevant industry experience. Demonstrated expertise verifying complex digital ASICs with track record of successful silicon tapeouts. Deep knowledge of ASIC verification flows with SystemVerilog and UVM including testbench architecture, verification planning, and coverage-driven methodologies. Experience developing verification environments from scratch and bringing

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