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TFT Panel Design Engineer

Apple - Cupertino, United States of America

Posted Mar 16, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work
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Application

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Deadline
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About this role

TFT Panel Design Engineer Cupertino, United States of America Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something. Apple is looking for a world-class Thin Film Transistor (TFT) panel design engineer to design, develop and launch the next display technologies for the displays in Apple products. The TFT panel design team is responsible for delivering the advanced TFT panel designs and technologies to enable the world's best display performance in Apple Products. Individual will serve as a focal point in architecting and developing the total TFT pixel and panel designs. This includes display panel modeling, simulation, integrated circuit-on-glass design, panel architecture, and whole panel function simulation. TFT panel architecture scoping and definition TFT device design, modeling, simulation and characteristics measurement Pixel and panel design, layout and parasitic parameter extraction TFT Pixel and panel modeling, characterization, and validation On-glass integrated circuit design, simulation and validation Failure mode analysis, root

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