Systems Signal Integrity Engineer - Apple Data center

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

87% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

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About this role

Systems Signal Integrity Engineer - Apple Data center Austin, United States of America Apple is seeking an enthusiastic signal integrity engineer for the system technology team. The candidate will help with concept and feature development, rapid prototyping, The Datacenter organization is looking for an outstanding engineer to support the system-level signal integrity design, analysis and validation aspects of Data center products development. The candidate will work within the System Technology organization to support the system-level Signal Integrity (SI), analysis and validation aspects of data center products development. The candidate should have deep knowledge and familiarity with all aspects of signal Integrity for high speed Serdes, electrical-optical-electrical signaling interfaces deployed in data center products. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. And the candidate is expected to work closely with System Design teams to provide detailed SI strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the all signal path. The roll includes the SI support through the specific project design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with relevant industry level work experience. Familiarity with all aspects of Signal Integrity for high speed SerDes, parallel bus, single ended signaling. Familiarity with all aspects of electrical-optical-electrical interface. Ability

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