SoC Power Flow Methodology Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

$140K-$258K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

71% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

SoC Power Flow Methodology Engineer Austin, United States of America Are you passionate about crafting solutions to intricate challenges? Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple's next-generation chips! Responsible for developing and improving low-power flow algorithms using AI and machine learning, which significantly impacts the work of many designers involved in mobile system-on- chips. In this role, you'll develop innovative automated tools and capabilities for the Silicon Engineering Power team. Your contributions will enable the creation of chips with unprecedented power efficiency. You'll be involved in the architecture, implementation, and validation of advanced low-power design and verification workflows. Additionally, you'll shape low-power strategies for emerging technologies. Your responsibilities will encompass the development of flows and tools for power analysis, optimization, and verification, seamlessly integrated into stages such as RTL development/ verification, synthesis, or place-and-route (P&R). You'll actively leverage various AI tools to innovate new solutions and enhance existing ones. Additionally, you'll collaborate with design teams to address queries, resolve issues, and ensure the smooth adoption of these methodologies. Minimum Qualifications: A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience Preferred Qualifications: Solid grasp of VLSI designs and SOC design processes. Enthusiasm for scripting and leveraging low-power expertise to innovate software solutions. Enthusiasm for leveraging AI/ML to innovate low-power methodologies and flows. Experience in flow development and algorithm design using Python/Perl/TCL.

Read the full description at jobs.apple.com. FewerJobs shows a preview and links to the original posting.