Silicon Validation Software Engineer: CPU and Memory Hierarchy

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Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Silicon Validation Software Engineer: CPU and Memory Hierarchy Austin, United States of America Would you like to work on SW that runs on every Apple phone, pad, and Mac computer in the world? Join our team of experienced SW engineers and debuggers in validating Apple's world class silicon. In this highly visible role you will be writing functional validation SW for the CPUs, caches, and memory subsystem of our SoCs, with the aim of identifying logic design and circuit bugs. You will be a SW developer for a system validation tool used widely across Apple's Silicon Engineering group, and will collaborate with SoC design and product engineering teams to debug and drive silicon issues to root-cause. Validate CPU cores, cache coherency, and memory hierarchy behavior on post-silicon platforms. Develop targeted stress tests to expose incorrect behavior under varying operating conditions(voltage, frequency, and temperature). Partner with design and architecture teams to correlate silicon behavior with intended micro architectural design. Catch incorrect silicon behavior and issues before product release. Identify sensitivity to PVT shifts, including incorrect behaviors and intermittent failures. Collect and analyze silicon data (logs, counters, traces) to understand system behavior across operating conditions. Provide actionable feedback to PVT and other teams to refine operating limits Minimum Qualifications: BS in Computer Science, Electrical Engineering, Computer Engineering, or related field with a minimum of 3 years relevant industry experience. Experience in post-silicon validation, PVT, system bring-up, or silicon debug. Preferred Qualifications: Strong understanding of CPU microarchitecture, cache coherency, and memory hierarchy. Knowledge

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