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Silicon Validation Software Engineer: CPU and Memory Hierarchy

Apple - Austin, United States of America

Posted Jan 6, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
Not verified
Verification
Not verified checked Jun 13, 2026
Salary
$147K-$272K From the posting source checked Jun 20, 2026
401(k) match
Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)
$116,543 U.S. median for this role
Projected growth (BLS Employment Projections)
+9.8% - Much faster than average

80% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function
Engineering From the posting source checked Jun 20, 2026
Seniority
Mid From the posting source checked Jun 20, 2026

Schedule

Shift type
Not verified
Weekend work
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Company

Equity
Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter
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Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

Silicon Validation Software Engineer: CPU and Memory Hierarchy Austin, United States of America Would you like to work on SW that runs on every Apple phone, pad, and Mac computer in the world? Join our team of experienced SW engineers and debuggers in validating Apple's world class silicon. In this highly visible role you will be writing functional validation SW for the CPUs, caches, and memory subsystem of our SoCs, with the aim of identifying logic design and circuit bugs. You will be a SW developer for a system validation tool used widely across Apple's Silicon Engineering group, and will collaborate with SoC design and product engineering teams to debug and drive silicon issues to root-cause. Validate CPU cores, cache coherency, and memory hierarchy behavior on post-silicon platforms. Develop targeted stress tests to expose incorrect behavior under varying operating conditions(voltage, frequency, and temperature). Partner with design and architecture teams to correlate silicon behavior with intended micro architectural design. Catch incorrect silicon behavior and issues before product release. Identify sensitivity to PVT shifts, including incorrect behaviors and intermittent failures. Collect and analyze silicon data (logs, counters, traces) to understand system behavior across operating conditions. Provide actionable feedback to PVT and other teams to refine operating limits Minimum Qualifications: BS in Computer Science, Electrical Engineering, Computer Engineering, or related field with a minimum of 3 years relevant industry experience. Experience in post-silicon validation, PVT, system bring-up, or silicon debug. Preferred Qualifications: Strong understanding of CPU microarchitecture, cache coherency, and memory hierarchy. Knowledge

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