Power Integrity Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$120K-$210K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

42% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Power Integrity Engineer Austin Metro Area, United States of America Do you like to work on groundbreaking technologies that enable amazing new products? Do you have the attention for details and love for precision to work towards an outstanding result? We are looking for a dedicated and passionate SoC Power Integrity Engineer to join our team in Hardware Technology Group. In this role, you will be responsible for the development, implementation, and verification of Power Integrity solutions for SoCs used in Apple devices (iPhone/iPad/Mac etc.). You will work with cross-functional teams to define off-die droop budgets, design and implement an end-to-end power delivery network (PDN) solution throughout PMU/PCB/PKG/Interposer/Die, and verify the quality of the power integrity using lab measurements. • Power delivery modeling, simulation, and characterization for die, interposer, package, board, and Voltage Regulator. • Close collaboration with multi-functional teams to design end-to-end power delivery systems for both current and future generations. • Definition of the PDN architecture and design solution space for the target system • Broad responsibility on all SoC droop related topics, including on-die inrush, off-die droop budget, PDN sign-off, noise coupling analysis, voltage guard band, active droop mitigation etc. Conduct end-to-end simulation studies including modeling of die/interposer/PKG/PCB/PMU, to meet stringent impedance and voltage droop spec. Provide implementation guidelines and feedbacks to silicon, package, system design and other cross-functional teams. Perform feasibility study for silicon floorplan, advanced droop mitigation schemes, voltage regulator modeling and tuning, system mockup design etc. Perform model to hardware correlation on component and

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