PLL Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$181K-$318K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

114% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

PLL Design Engineer Sunnyvale, United States of America We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal candidate will possess strong analytical abilities, a passion for innovation, and extensive experience in designing and implementing PLL architectures and circuits. In this highly visible role, you will drive innovation within a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. Our team is responsible for all aspects of silicon development for cellular transceivers, with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level. You will utilize your virtuoso knowledge to design PLL Circuits and component blocks including some of the following: PLL, VCO, LO generation, Dividers, Charge Pumps, XTAL, and other RF/mixed-signal blocks. In addition to the above responsibilities, you will utilize your technical analysis skills to conduct transistor-level feasibility studies for new RF circuit architectures, as well as be responsible for simulation and modeling to design and develop analog and mixed signal solutions for next-generation wireless chips. As an PLL design engineer, you will be responsible for providing clocking solutions for cellular transceiver chips. Responsibilities include: Working with platform architects, system, and digital design groups to define the requirements for PLL and its sub-blocks based on the system requirements. Collaborating with the technology team on process selection for the target device. Driving transistor-level feasibility studies of RF/mixed-signal circuit blocks and architectures. Designing various component

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