PHY RTL Design Engineer

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

PHY RTL Design Engineer Irvine, United States of America Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Develop signal processing intensive design for wireless communication SoCs, including: Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols. RTL coding and verification for PHY modem development. Support banckend activities by reviewing the reports and appropriate adjustment of the design. Involve in the pre and post silicon bringup process. Minimum Qualifications: Bachelors degree +10 years of relevant experience in related field. Strong understanding of DSP. Digital Communications knowledge. Proficiency in RTL Design. Preferred Qualifications: Familiarity with UVM DV environment and AI based efficiency improvement flows. Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications. Understanding of Decoders - Viterbi, LDPC, Polar. Understanding of Filter design, multi-radix implementation,

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