PHY Design Verification Engineer

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

PHY Design Verification Engineer San Francisco Bay Area, United States of America Would you like to join Apple's growing wireless silicon development team? Our wireless SoC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact with DV methodologists, designers, and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification, ensuring the highest design quality. Work closely with the system and design teams to review and understand the PHY subsystem microarchitecture, and create verification plans from specifications, review and refine to achieve coverage targets. Build block/subsystem level test benches with a reference model, using the best-in-class DV methodology. Architect test benches with maximum reusability in mind. Develop and execute both directed and constrained random tests, debug failures, manage bug tracking, and work

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