Packaging Substrate Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Mental health support

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work

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About this role

Packaging Substrate Engineer San Francisco Bay Area, United States of America Our Hardware Technology Packaging team invents, designs, develops, and integrates electronic packaging solutions for Apple's internal and custom external components of hardware for its consumer electronic products such as iPhone, iPad, Mac, Apple Watch, Apple TV etc. In this highly visible role, you will own and drive sophisticated package selection, new-generation package structure and configuration optimization. You will be responsible for Apple package substrate including design, technology, manufacturing, and reliability, and future roadmap; and work with cross-functional teams to achieve the best package performance. Lead SoC package substrate technology development, pathfinding, and roadmap definition. Work with substrate manufacturing industry, foundry, and OSAT to bring package substrate solution from concept to HVM. Drive industry with sophisticated package solutions, new architecture, material and process development, and spec definitions. 5% International travel Work with industry partners to develop new substrate technologies from concept to HVM for Apple packaging roadmap. Work with cross-functional groups to define & optimize new package substrate architectures based on performance, technical risk, cost, and availability etc. Problem solving of technical issues during the full product development cycle. Minimum Qualifications: Minimum requirement of a bachelors degree Preferred Qualifications: MS and or Ph.D. and 3+ years of relevant industry experience. In-depth knowledge of substrate technology, manufacturing process, design rules, and roadmap. Hands-on experience in substrate manufacturing and technology development: Cu plating, lithography, dielectric material, via formation, solder resist, surface finish etc. Familiarity with package assembly and integration process preferred. Experience

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