Package Integration Engineer
Apple - San Francisco Bay Area, United States of America
Posted Mar 17, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Package Integration Engineer San Francisco Bay Area, United States of America Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets. • In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. • We are looking for individuals who are very innovative with a proven track record to Define new package characteristics based on unique module and system level performance, cost, and footprint requirements. Define package/packaging specifications. Work with suppliers on package design, new material, new equipment selection and process/process flow development. Perform initial proof of concept sample build, POR establishment, package and process qualification, reliability test, yield analysis and enhancement. Coordinate with other packaging and cross-functional team members to comply with product development/ramp schedule. Deliver package/packaging milestones on time. Define packaging roadmap based on long term packaged product requirements. Work closely and Manage suppliers' R&D activities. Minimum Qualifications: BS and 10+ years of relevant industry experience. Preferred Qualifications: M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus. Some hands-on knowledge in Wafer Bumping, Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach (including multilayer thin die stacking), encapsulation/molding, under-fill, ball attach, package singulation and Tape
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