Integration Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

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About this role

Integration Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal candidate will have experience in ASIC design with: • IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, GPU, memory controllers, custom logic) into a SoC. • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented. • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects. • Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to

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