IC Package Design Engineer
Apple - Austin Metro Area, United States of America
Posted May 4, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
IC Package Design Engineer Austin Metro Area, United States of America Our Packaging team defines, designs, and integrates advanced electronic packaging solutions for Apple's internal and custom components across products including iPhone, iPad, Mac, Apple Watch, and Apple TV. We're looking for a Package Design Engineer to drive the physical design and integration of advanced semiconductor packages across SoC, memory, RF, and cellular technologies. You will play a key role in shaping the architecture, scalability, and efficiency of next-generation products while advancing design methodologies through automation and AI. As a Package design engineer, you will lead advanced package architecture, drive next-generation package structure and configuration optimization, and own Package/SiP/module physical design from concept through tape-out. You will collaborate closely with cross-functional teams to deliver optimized SI/PI performance across a wide range of silicon technologies You are expected to leverage AI tools to enhance design efficiency, quality and performance. Perform physical layout of package substrates for diverse silicon, including System-on-Chip (SoC), Memory, RF, and cellular integrated circuits (ICs). Execute parasitic extraction (RLGC) and S-parameter modeling to validate that package designs meet Signal and Power Integrity (SI/PI) performance targets. Lead cross-functional collaboration on package feasibility and system co-optimization; align with Product Design on chip floorplan, System Architecture on package configuration, and Silicon/SIPI teams on electrical performance. Drive package design methodology improvements by evaluating new CAD tools and developing automated design and verification flows to enhance efficiency and streamline the release process. Minimum Qualifications: BS and 10+ years of relevant industry experience Preferred
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