Graphics Power Analysis & Optimization Engineer
Apple - Austin, United States of America
Posted Apr 14, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Graphics Power Analysis & Optimization Engineer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices! We are looking for a talented and creative engineer to support the power activity of Apple best-in-class GPU development. For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on GPU designs: - Create early power estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power rollup and analysis. - Analyze various GPU workloads to identify power reduction opportunities. - Evaluate and implement power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage. - Develop flows & heuristics to accelerate power triage on large power data sets. Minimum Qualifications: Experience with Verilog and SystemVerilog. Experience with scripting in Python. Minimum requirement of BS degree. Preferred Qualifications: Knowledge of digital logic design principles including power and timing implications. Experience with VLSI power fundamentals: dynamic & leakage. Experience with low power design: clock gating, data-gating. Excellent communication
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