Graphics Post silicon Test & Methodology Engineer
Apple - Austin, United States of America
Posted May 11, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Graphics Post silicon Test & Methodology Engineer Austin, United States of America Do you love creating solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, large subsystems. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll craft and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this role, you will be a cross functional liaison responsible for Pre-silicon inputs and debug on post-silicon to enable implementation, validation, and improvement of power efficiency in our GPU designs. Are you a competent problem solver who thrives under pressure to find creative time critical solutions to chart the future of GPU designs at Apple? If so, we would love to hear from you. You will isolate post-silicon issues into Test, Process, Design or interactions, drive stop gaps using PFA/EFA, and make corrective actions in future designs. Ensure manufacturing deliverables for Power/LVcc Design targets and work on power optimization by collaborating with Product and Silicon Validation teams You will compare and close Post-silicon to Design targets You will drive GPU inputs into Product, Test and Silicon Validation teams Minimum Qualifications: Experience in DFT - ATPG and BIST Device physics experience Perl or Python coding experience BS + 3
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