Formal Verification - AI/ML Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

$181K-$318K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

114% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Formal Verification - AI/ML Engineer Austin, United States of America Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the intersection of Artificial Intelligence and Formal Verification. In this role, you will explore, prototype, and build AI-powered systems - with a focus on Large Language Models - to augment and transform how formal verification is performed on Apple Silicon. You will work closely with formal verification engineers, design engineers, and EDA tool developers to identify high-impact opportunities and deliver practical, domain-specific AI applications. You will be responsible for: Building domain-specific AI applications that leverage LLMs and other ML techniques to accelerate formal verification workflows - from specification interpretation to property generation, proof debugging, and beyond. Developing and fine-tuning LLM-based systems tailored to hardware verification tasks, including retrieval-augmented generation (RAG) pipelines, agentic tool-use frameworks, and domain-adapted models. Collaborating with formal verification engineers to deeply understand FV methodologies, pain points, and opportunities where AI can meaningfully improve productivity, quality, and coverage. Prototyping novel AI-driven approaches for tasks such as automatic SVA property synthesis, natural-language-to-formal-specification translation, proof strategy recommendation, and intelligent counterexample analysis. Evaluating and integrating emerging AI/ML research into practical, production-quality tools and workflows used by the FV team. Establishing best practices and infrastructure for AI application development within the FV organization. Minimum Qualifications: A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience. Preferred Qualifications: Strong hands-on experience building AI/ML applications, particularly those leveraging Large Language Models

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