DRAM Design Validation Engineer
Apple - Cupertino, United States of America
Posted Apr 13, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
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- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
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Where they hire
State eligibility is not yet verified.
About this role
DRAM Design Validation Engineer Cupertino, United States of America Do you love crafting elegant solutions to highly sophisticated challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. As our DRAM Design Validation Engineer, you will be ensuring the successful integration of DRAM memories with SoC devices. Work with our design, verification and integration engineers to ensure memory controller and PHY requirements are well defined and cover the scope of DRAM based corner cases. Collaborate with Architecture, MCU, DDRPHY and DRAM vendors for Apple's main memory feature. Ensure DRAM simulation meets Apple's requirements. Ensure the internal and external DRAM silicon and package level testing needs are met. Debug RMA material with apparent DRAM related defects. Collaborate with the DRAM vendors to improve the DRAM performance and power on Apple systems. Drive the roadmaps and specs of memory vendors for next technology node devices. Minimum Qualifications: PhD or MS or BS Degree with 5+ years in DRAM development Preferred Qualifications: Expert in DRAM cell architectures Expert of DRAM memory organization and periphery design for low DRAM power Expertise in DRAM simulation Experience in memory interface verification with understanding DDR-PHY
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