FewerJobs.
All jobs

CPU Design Timing Engineer

Apple - Beaverton, United States of America

Posted Apr 14, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
Not verified
Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
Not verified
Relocation assistance
Not verified
Childcare support
Not verified
Learning budget
Not verified
Verification
Not verified last checked Jun 13, 2026
Salary
Not verified not verified - source not recorded; timestamp not recorded
401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

Was this benefit information wrong? Tell us.

Schedule

Shift type
Not verified
Weekend work
Not verified

Application

Cover letter
Not verified
Assessment
Not verified
Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

CPU Design Timing Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure. As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to: • Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU. Minimum Qualifications: Minimum BS and 10+ years of relevant experience Experience with a static timing analysis tool such as PrimeTime® or Tempus® Experience with timing analysis with multiple clock and power domains, noise analysis, and fixing noise in designs Experience with variation modeling

Read the full description at jobs.apple.com. FewerJobs shows a source-linked preview and links to the original posting.

Apply at jobs.apple.com

Apply link not verified; last-live date unavailable.

What verified means

Verified means a displayed claim has a recorded source field, a source URL when available, and a timestamp showing when FewerJobs checked or enriched the evidence.

Related jobs