CAD Engineer – Design Verification Methodology

Benefits

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Family-building benefits

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Verification

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Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Application

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About this role

CAD Engineer – Design Verification Methodology Austin Metro Area, United States of America Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems. Minimum Qualifications: Minimum of BS degree + 10 years of relevant experience Experience developing, maintaining, and enhancing an existing system for regressing RTL Experience debugging vendor tool problems Python programming

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