ASIC Power Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 13, 2026

Salary

$172K-$302K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

103% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Power Engineer Los Angeles Metro Area, United States of America Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient / low-power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering teams. In this highly visible role, you will be at the center of low-power architecture, power modeling and correlation efforts with a critical impact on getting functional products to hundreds of millions of customers quickly. You will work on power modeling, analysis and correlation tasks for wireless communication SoCs. Will you join us and do the best work of your life here? Define power-efficient SOC architecture and schemes, write power spec. Estimate pre-silicon power, build wireless application and atomic power model with high accuracy. Define and generate power vectors with Design and DV support. Collect pre-silicon power data using power flow and tools. Analyze and identify power reductions. Support post-silicon power correlation. Minimum Qualifications: BS and 10+ years of relevant experience. ASIC power knowledge. Experience with Power tools, e.g. PTPX and Power Artist. Understand ASIC logic design. Knowledge of low power design and UPF. Proficiency in scripting languages (Shell, Perl or Python). Basic knowledge on common SOC components, e.g. CPU, fabric, peripherals and PCIe. Strong problem solving and analytical skills. Preferred Qualifications: Pre-silicon power estimation experience. Pre-silicon Power modeling experience. Actual low

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