Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer

Verified benefits

Parental leave

6 weeks source

Non-birth-parent leave

6 weeks

Verified

Yes last checked 2026-05-07

Salary

Not disclosed

Market context

Median wage (BLS OEWS)

$116,543 national median

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Where they hire

State eligibility is not yet verified.

About this role

Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer 2 Locations Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer /job/US-NC-Durham/Staff-Engineer---Digital-ASIC-and-Signal-Processing-Chip-Architect-Systems-Engineer_R260551-1 2 Locations Posted 30+ Days

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