Staff Engineer - DFT
Ambiq Micro INC - Singapore
Posted Oct 17, 2025
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
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- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Staff Engineer - DFT Singapore Company Overview Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 290 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us - the intelligence everywhere revolution starts here. Responsibilities Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools. Develop and implement low-power DFT architecture and infrastructure. Generate structural test vectors, analyse, and improve coverage, test time and test cost. Perform pre/post-layout scan and MBIST simulations. Work with designers on STA, physical, power and logical issues related to DFT. Work with test engineers to bring up test vectors on silicon. Qualifications BS/MS in ECE/EE and at least 10 years of experience in DFT implementation. Skilled in different types of DFT structures, including
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