Sr. ASIC Design Verification Engineer, Amazon Leo

Benefits

Parental leave

6 weeks From the posting source

Non-birth-parent leave

6 weeks From the posting source

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$159K-$215K From the posting source

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

67% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Senior From the posting source

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Sr. ASIC Design Verification Engineer, Amazon Leo Austin, Texas, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. The Role: Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models · Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program · Participate in the validation of ASIC implementations in Verilog/SystemVerilog · Run formal verification of complex blocks to ensure functional correctness · Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C · Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database Export Control Requirement: Due to applicable export control laws and regulations, candidates must be

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