Sr. ASIC Design Verification Engineer

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Verification

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Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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About this role

Sr. ASIC Design Verification Engineer San Jose, California, US The application window is expected to close on: Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Participate in the ASIC design verification for Cisco high-end switching products. Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis. Construct testbenches components like scoreboard, agents, sequencers, and monitors. Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration Ensure comprehensive verification coverage through code and functional coverage implementation and review Minimum Qualifications: Bachelor's degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience. Prior experience in System Verilog and UVM. Experience with ASIC design and verification processes, debugging,

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