Manager, ASIC Sustaining Engineering, Silicon Operations

Benefits

Parental leave

6 weeks From the posting source checked Jun 20, 2026

Non-birth-parent leave

6 weeks From the posting source checked Jun 20, 2026

Family-building benefits

• Fertility benefits: Offered From the posting source checked Jun 20, 2026
• Adoption assistance: Offered From the posting source checked Jun 20, 2026
• Surrogacy assistance: Offered From the posting source checked Jun 20, 2026

Mental health support

Offered From the posting source checked Jun 20, 2026

Relocation assistance

Not verified

Childcare support

Offered From the posting source checked Jun 20, 2026

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$149K-$201K From the posting source checked Jun 20, 2026

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

50% above the BLS role benchmark for software engineering aggregate.

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Manager, ASIC Sustaining Engineering, Silicon Operations Sunnyvale, California, USA The ASIC Sustaining Engineer has the responsibility for Yield improvement to meet or beat target and Root Cause Analysis for Yield excursions across Wafer, Assembly and Test. Use statistical tools and data analysis to identify yield limiters and trends in electrical test and in-line inspection data. Conduct failure analysis (FA) on defective wafers and devices to identify the source of, or prevent, yield excursions. Design and execute experiments (DOE) to optimize manufacturing processes and reduce particle contamination. Partner with process, equipment, and design engineers to implement solutions to improve, maintain, or troubleshoot production lines. Install, qualify, and maintain in-line defect inspection and review equipment. Create and maintain specifications, process documentation, and best-known methods Key job responsibilities Lead team to identify root cause for chip performance / yield / quality issues. Analyze CP test bin / data log to identify failure mode. Electrical failure analysis and physical failure analysis to locate suspect process stage Work with appropriate supplier to define corrective actions / solutions. Trace action implementation to verify effectiveness. Product early-stage design support to help product tape-out smoothly and Si success: Design rule review & assessment for robust product design Layout review or DFM to enlarge manufacturing window Yield window characterization and device sweet spot identification for the best yield / performance process condition. Basic Qualifications: - 5+ years of technical product or program management experience - 7+ years of working directly with engineering teams experience - 3+ years of software

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