FPGA Engineer, Amazon Leo Government

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

43% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

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Where they hire

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About this role

FPGA Engineer, Amazon Leo Government El Segundo, California, USA Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. Innovation is part of our DNA! Our goal is to be Earth's most customer centric company, and we are just getting started. We need people who want to join an ambitious program that continues to push the state of the art in distributed systems and hardware design. As an FPGA engineer on the Leo Government Solutions team you will create FPGA solutions to support Amazon Project Kuiper's satellite communication system. This is a unique opportunity to define a new system with few legacy constraints. You will work with systems and algorithm teams to define/develop/implement/test/release FPGA-based solutions to enable Project Kuiper. In particular, your work will power high-speed communication links while making use of the latest generations of FPGA technologies, design processes, and tools. You will tackle challenging, novel situations every day and have the opportunity to work with multiple technical teams at Amazon in different locations, partner teams, and end customers. 10037 Key job responsibilities - Create and release FPGAs through the development phases of uArchitecture-RTL Design-Physical Implementation-Timing Closure-Simulation Validation- Lab Based Silicon Validation. - Collaborate with RF and Optical Communications and Signal Processing system architects and design engineers to define, design, implement, and test modem and digital logic functions in FPGA technology. - Writing RTL code, developing testbenches, performing simulation and

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