DFT Design Engineer I, AWS Machine Learning Acceleration

Benefits

Parental leave

Not verified not verified - source not recorded; timestamp not recorded

Non-birth-parent leave

Not verified not verified - source not recorded; timestamp not recorded

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified

Salary

Not verified not verified - source not recorded; timestamp not recorded

401(k) match

Not verified

Was this benefit information wrong? Tell us.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

DFT Design Engineer I, AWS Machine Learning Acceleration Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. As a member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll contribute to the application of new technologies to large scale server deployments in a continuous effort to deliver a world-class customer experience. This is a fast-paced, intellectually challenging position, and you'll work with thought leaders in multiple technology areas. You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve your products performance, quality and cost. We're changing an industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today. Key job responsibilities • Develop, implement and verify state-of-the-art Design for Test (DFT) architectures • Work with block designers to integrate DFT implementations • Work with physical design team to setup and implement DFT insertion flow • Develop high coverage and cost effective DFT methodologies • Perform RTL coding and Verification • Participate in Silicon debug and write scripts to effectively handle ATE related data • Communicate and work

Read the full description at www.amazon.jobs. FewerJobs shows a source-linked preview and links to the original posting.