ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Benefits

Parental leave

6 weeks From the posting source

Non-birth-parent leave

6 weeks From the posting source

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Source-linked checked Jun 7, 2026

Salary

$157K-$213K From the posting source

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

65% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

Not verified

Weekend work

Not verified

Company

Equity

Offered Verified - SEC 10-K source

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Cupertino, California, USA Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world. We have data center locations in the U.S., Europe, Singapore, and Japan, and customers across all industries. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer, you will: • Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications and targets • Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs between features, power consumption, performance, and area requirements • Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs with appropriate constraints • Execute lint and clock domain crossing quality checks to ensure design integrity • Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts The ideal candidate

Read the full description at www.amazon.jobs. FewerJobs shows a preview and links to the original posting.