Silicon Ranch jobs

Silicon Architect, AI Power and Performance San Diego, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. This role offers the opportunity to work on cutting-edge power management technologies for AI/ML workloads that directly impact the battery life and efficiency of Google's flagship Android devices and custom silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the analysis and implementation of architectural optimizations that span the full stack - from low-level silicon IP to high-level Android frameworks - to maximize AI performance per watt. Influence hardware and software roadmaps for SOC, AI accelerators, and emerging memory technologies to meet future Gemini and GenAI product requirements. Propose and drive the development of proof-of-concept prototypes for next-generation power management frameworks and specialized AI solutions. Act

Silicon DFT Engineer, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition,

Senior Silicon Diagnostics Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Silicon Diagnosis and Defect Isolation: Perform post-silicon electrical and physical fault isolation using production test results (e.g., error logs, flop mapping, and software-based diagnosis) to narrow down the cone of logic. Methodology Development: Develop, deploy, and automate volume diagnosis and data analysis flows. Generate and apply specialized diagnosis patterns for Soft-Defect-Location (SDL) or Laser-Voltage-Imaging (LVI). Cross-Functional Collaboration: Partner with Design, DFX, Verification, and Test teams to define requirements for highly diagnosable designs and to build layout databases for diagnosis and cross-probing. EFA and Root Cause Analysis: Define and execute Electrical Failure Analysis (EFA) workflows to root-cause yield issues, qualification failures, and customer returns. ATE and Pattern Debug: Lead silicon bring-up, debug, and validation of DFT features on Automated Test Equipment (ATE), debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues. Minimum qualifications: Bachelor's degree in Electrical Engineering,

Silicon Validation Engineer, HBM, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role you will work on test design, bring-up, triage, and debug of the TPU High Bandwidth Memory (HBM) subsystem across emulation, test chip, and production silicon platforms. You will work closely with Silicon Validation, HBM technologists, and pre-silicon teams during the development phase of the ASIC life-cycle, ensuring proper features are in place for post-silicon validation and debug. Once silicon is in the lab, you will collect and help interpret data alongside system software and software test infrastructure developers to ensure the HBM subsystem has met the threshold for production release. You will help develop processes and tests to ensure smooth and reliable performance of HBM projects. You will be direct throughout the project lifecycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug. By leveraging silicon knowledge you will develop and operate software-based tests for full investigation of HBM operation. You will work closely with

Silicon Engineering Intern, PhD, Summer 2026 Bengaluru, Karnataka, India; +1 more As a Silicon Engineering Intern, you will work in a team that is shaping the future of Google Cloud Silicon, including TPUs, arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements and manages the hardware, software, machine learning and systems infrastructure for all Google services (e.g., Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers, and people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest Cloud Silicon products to running a global network, while driving towards shaping the future of hyperscale computing. Google is and always will be an engineering company. We hire people with a broad set of technical skills who are ready to address some of technology's greatest challenges and make an impact on millions, if not billions, of users. At Google, engineers not only revolutionize search, they routinely work on massive scalability and storage solutions, large-scale applications and entirely new platforms for developers around the world. From Google Ads to Chrome, Android to YouTube, Social to Local, Google

Silicon CAD Engineer, University Graduate, PhD Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on chips powering the next generation of Google Cloud systems. You will work well both separately and as part of a team. In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed Electronic Design Automation (EDA) tools, custom tooling, and emergent technologies from GDM and core. The AI and Infrastructure team is redefining what's possible. We empower

Front-End CAD and IP Management Engineer, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will serve as the critical link between IP development and SoC integration. You will be responsible for defining and executing the qualification standards that ensure third-party and internal IPs are ready for high-performance silicon designs. You will be developing automated front-end CAD flows, managing complex EDA tool collaterals, and collaborating with cross-functional teams to resolve technical integration bottlenecks. By streamlining the delivery process through advanced scripting and dashboarding, you will directly enable the team to hit dynamic tape-out schedules with high-quality, reliable silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the delivery of Silicon Internet Protocol (IP) to design teams to

Silicon Validation Engineering Manager, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Validation Engineering Manager, you will lead the group focused on custom TPU silicon. You will set strategy and co-ordinate resources, planning, and execution for the team. You will strategize, review, and execute test plans for silicon systems and subsystems. You will own silicon bringup, new product introduction (NPI), and sustaining efforts. You will serve as the central co-ordination point between your team and systems teams, including hardware, software, manufacturing, and supply chain. You will also manage relationships with vendors and contract manufacturers. You will verify that silicon meets functional and performance requirements and own qualification, characterization, and deliverables for post-silicon, including interfaces, compute cores, power, and performance. You will debug issues, suggest fixes, and ensure silicon meets quality and reliability requirements throughout the entire product life-cycle (PLC). The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure

Head of Silicon Systems and Architecture, XR San Jose, CA, USA; +1 more The XR team at Google is building the future of immersive and augmented computing. We are a fast moving team with engineers, designers, and research scientists tasked to build the next generation technology to shape people's way of living in new imaginative ways. Through the development of Galaxy XR, Smart Glasses prototypes, and ARCore we are enabling augmented reality experiences around the world. But we aren't stopping there. We are working on really cool, technologies enabling the next generation of immersive and augmented experiences, through collaborations with teams across Google and our third-party partners. As the Head of Silicon Systems and Architecture, you will serve as the primary architect and multiplier for our silicon partnerships. You will define the hardware foundations through silicon for the next generation of headsets and glasses, ensuring that future chipsets are vertically integrated with Google's perception and software stacks to deliver user experiences. For decades, the computing revolution has reshaped our world driven by breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap - the convergence of AI and XR. This is more than just new devices - it's about reimagining how we interact with the world around us. We're building a future where lightweight XR devices like smart glasses and headsets pair with helpful AI to augment human intelligence, offering personalized, conversational, and contextually aware experiences. Individual pay is determined

Silicon Validation Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be helping in bringing custom Application-Specific Integrated Circuits (ASICs) from concept through to production. You will be a part of the silicon validation effort of the overall silicon product development lifecycle. Your efforts may center on power features, interfaces, HBM memory, compute functionality, or various aspects of system performance. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development

Senior Silicon Validation Engineer, Volume Production and Yield New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. We are seeking a highly motivated and experienced Silicon Engineer to drive our Volume Production and Yield efforts. In this pivotal role, you will be the primary technical owner for the transition of our silicon designs into high-volume factory manufacturing, delivering screening packages to factory partners and driving continuous silicon yield monitoring, failure analysis, voltage margin characterization, and improvement across the product lifecycle. You will leverage AI-driven data analytics and machine learning techniques to optimize yield, accelerate failure debug, and enhance overall silicon quality. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Provide technical guidance and expertise for volume productization and post-silicon yield enhancement. Define and deliver silicon screening packages to factory organizations. Execute and refine the silicon yield management strategy, leading failure analysis, root cause debug of limiters, and production data analysis. Leverage AI/ML tools

Technical Program Manager III, Silicon Development, Technical Infrastructure Sunnyvale, CA, USA Google's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers. Using your extensive technical and leadership expertise, you manage projects of various size and scope, identifying future opportunities, improving processes and driving the technical directions of your programs. As the Silicon Development Technical Program Manager, you will support Google's custom silicon for AI by managing custom silicon development programs. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by factors including job-related skills, experience, and relevant education

DFT Engineer III, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition,

Senior Silicon Validation Engineer, CPU Tel Aviv, Israel; +1 more Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. As a Silicon Validation Engineer at Google Cloud, you will play a pivotal role in the validation of Google's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. With your expertise in post-silicon validation, you will be identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini

Lead Engineer, Silicon and Software Integration, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be working on ASIC development, validation, software, tools, and methodologies and will have the ability to push the boundaries of chip-development and hardware/software integration and validation. You will own cross-functional work streams focussed on end-to-end HW/SW integration and validation to demonstrate HW, SW, and system functionality and performance. You will help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments. You will serve as a key bridge between specification, design, and verification teams as well as compiler and performance teams with technical depth and breadth across the ML compute IP. As a lead, you will own strategy, planning, validating, and delivering hardware and software systems which are shown to be functional and performant. You will be responsible for coordination, debug, and enablement of the platform. The AI and Infrastructure

Lead Technical Program Manager, Silicon Bengaluru, Karnataka, India A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. As a Senior Silicon Implementation Technical Program Manager (TPM) team, you will lead a team responsible for SOC development over the full product cycle from pre-silicon to commercialization. You will have a strong understanding of IP and SoC delivery in an exceptional silicon team. You will bring a breadth of expertise across silicon architecture, RTL, Design Verification (DV), Physical Design (PD), etc. to enable silicon productization. You will drive execution of multiple concurrent SoC projects, this includes coordination of deliverables across multiple geographies, managing overall program schedules at Power Performance Area (PPA) and quality, negotiations with stakeholders and escalation when needed to get decisions made and dissemination of program status across the team. You will need to have excellent written and verbal communication skills and relationship building across stakeholders. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the

Junior Silicon DFT Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG),

AI/ML Silicon Validation Lead, Google Cloud, TPU Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The Platform Enablement team is responsible for the development, bring-up and qualification, deployment, sustaining the quality of our AI/ML custom silicon. We plan and integrate hardware and software stacks and operate them on emulation, simulation and post-silicon platforms. We work closely with silicon design, platform hardware, firmware and software teams to enable on-time delivery of high quality silicon products. As a Manager, you will be responsible for growing the team through hiring, developing a psychologically safe environment for the team to succeed, enabling people development through effective career conversations, mentoring and building a strong community. In this role, you will be working on building, managing and leading a team of engineers responsible for post-silicon validation of AI/ML SoC which uses technology, working closely with the architecture, design, verification, firmware, software and platform leads, ensure timely silicon bring-up, enablement and debug closures and driving the preparation of necessary tests and collaterals for effective

Silicon Validation and Automation Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Run, monitor, and analyze nightly Continuous Integration (CI) regression results. Design and implement new regression methods and supporting infrastructure/Graphical User Interface (GUI). Identify, debug, and report issues while performing initial root cause analysis and routing to IP owners. Develop and maintain tools for silicon validation and debug. Maintain and enhance automation infrastructure for various regression cadences. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 1 year of experience in post-silicon validation, SoC debug, or a similar role. Experience with Continuous

Lead Silicon Validation Engineer Pune posted: Posted 18 Days Ago

Staff Engineer, Post-Silicon Validation (AI-Enabled Workflows) US, MA, Wilmington posted: Posted 23 Days Ago

Senior Post-Silicon Validation Engineer, Networking Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. We are building a new team to lead the post-silicon validation efforts for our cutting-edge product. We're looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact. As a Silicon Validation Engineer at Google Cloud, you'll play a pivotal role in the validation of Google's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale

Silicon Reliability Engineer Shanghai (JingAn) posted: Posted Today

Personal Banker - Universal- East Highlands Ranch CO - Highlands Ranch (80126) posted: Posted 11 Days Ago