Silicon Ranch jobs

Silicon Architect, AI Power and Performance San Diego, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. This role offers the opportunity to work on cutting-edge power management technologies for AI/ML workloads that directly impact the battery life and efficiency of Google's flagship Android devices and custom silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the analysis and implementation of architectural optimizations that span the full stack - from low-level silicon IP to high-level Android frameworks - to maximize AI performance per watt. Influence hardware and software roadmaps for SOC, AI accelerators, and emerging memory technologies to meet future Gemini and GenAI product requirements. Propose and drive the development of proof-of-concept prototypes for next-generation power management frameworks and specialized AI solutions. Act

Silicon Validation Engineer, HBM, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role you will work on test design, bring-up, triage, and debug of the TPU High Bandwidth Memory (HBM) subsystem across emulation, test chip, and production silicon platforms. You will work closely with Silicon Validation, HBM technologists, and pre-silicon teams during the development phase of the ASIC life-cycle, ensuring proper features are in place for post-silicon validation and debug. Once silicon is in the lab, you will collect and help interpret data alongside system software and software test infrastructure developers to ensure the HBM subsystem has met the threshold for production release. You will help develop processes and tests to ensure smooth and reliable performance of HBM projects. You will be direct throughout the project lifecycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug. By leveraging silicon knowledge you will develop and operate software-based tests for full investigation of HBM operation. You will work closely with

Senior Silicon Architect Mountain View, CA, USA The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google . Position reports to the Google Mountain View, CA office & may allow for a hybrid schedule as per Google policy. Artificial intelligence will be one of humanity's most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements. Utilize high-level performance and power models to guide architectural decisions and conduct detailed trade-off analyses to optimize for system-level goals. Create and maintain detailed architectural specification documents that guide micro-architecture and design teams throughout the project lifecycle. Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements. Drive the

Head of Silicon Systems and Architecture, XR San Jose, CA, USA; +1 more The XR team at Google is building the future of immersive and augmented computing. We are a fast moving team with engineers, designers, and research scientists tasked to build the next generation technology to shape people's way of living in new imaginative ways. Through the development of Galaxy XR, Smart Glasses prototypes, and ARCore we are enabling augmented reality experiences around the world. But we aren't stopping there. We are working on really cool, technologies enabling the next generation of immersive and augmented experiences, through collaborations with teams across Google and our third-party partners. As the Head of Silicon Systems and Architecture, you will serve as the primary architect and multiplier for our silicon partnerships. You will define the hardware foundations through silicon for the next generation of headsets and glasses, ensuring that future chipsets are vertically integrated with Google's perception and software stacks to deliver user experiences. For decades, the computing revolution has reshaped our world driven by breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap - the convergence of AI and XR. This is more than just new devices - it's about reimagining how we interact with the world around us. We're building a future where lightweight XR devices like smart glasses and headsets pair with helpful AI to augment human intelligence, offering personalized, conversational, and contextually aware experiences. Individual pay is determined

Silicon Validation Engineering Manager, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Validation Engineering Manager, you will lead the group focused on custom TPU silicon. You will set strategy and co-ordinate resources, planning, and execution for the team. You will strategize, review, and execute test plans for silicon systems and subsystems. You will own silicon bringup, new product introduction (NPI), and sustaining efforts. You will serve as the central co-ordination point between your team and systems teams, including hardware, software, manufacturing, and supply chain. You will also manage relationships with vendors and contract manufacturers. You will verify that silicon meets functional and performance requirements and own qualification, characterization, and deliverables for post-silicon, including interfaces, compute cores, power, and performance. You will debug issues, suggest fixes, and ensure silicon meets quality and reliability requirements throughout the entire product life-cycle (PLC). The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure

Silicon Product and Test Engineer Toronto, Ontario, Canada Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build . Within Proto, our Bitcoin Products team delivers the product and go-to-market strategy, software, firmware, and custom silicon needed to make Bitkey and our ambitious mining initiatives a reality. Come build the future of money with us! The Role We are looking for a Product & Test Engineer to drive post-silicon productization of our bitcoin mining ASICs from silicon bring-up through high-volume manufacturing. This role spans silicon characterization, yield optimization, test strategy development, correlation across multiple platforms, and system-level performance optimization. This is a highly cross-functional role working across ASIC Design, ATE, Bench, Systems, Reliability, Foundry, and OSAT partners. The ideal candidate is hands-on, data-driven, comfortable operating in ambiguity, and excited about building and scaling complex hardware products in a fast-moving environment. You Will - Drive post-silicon bring-up, characterization, qualification, and productization activities from first silicon through mass production. - Develop and optimize wafer sort (CP) and final test (FT) screening strategies to improve power, performance, yield, quality, and DPPM. - Develop, debug, and maintain ATE test

ML Accelerator Performance Validation Engineer, Post Silicon Validation Austin, Texas, USA Annapurna Labs, an AWS organization with development centers in the U.S. and Israel, builds custom silicon and software for AWS customers. Our team combines cloud-scale innovation with world-class expertise across silicon engineering, hardware design, verification, software, and operations to tackle technical challenges that have never been seen before. Join our Post-Silicon Validation team to quantify and qualify the performance of AWS's custom ML training chips against architectural targets. You'll bridge the gap between silicon capabilities and real-world ML workload demands - ensuring our accelerators deliver on latency, throughput, and efficiency promises at cloud scale. You'll work in a fast-paced, startup-like environment alongside some of the brightest minds in the industry on next generation AI/ML hardware that powers AWS's training and inference infrastructure. Your analysis will directly shape architectural decisions for next-generation accelerators and determine when silicon is ready for production deployment. Key job responsibilities Design and execute performance benchmarks spanning micro-architectures to full model training Measure and analyze compute throughput, memory bandwidth, interconnect latency, and more Profile real ML workloads (transformer models, LLMs, vision models) on silicon Identify performance bottlenecks and work with architecture teams on optimization Build automated performance regression dashboards and tracking infrastructure Correlate silicon measurements against RTL simulation and emulation predictions A day in the life Your primary focus is measuring and understanding how our AI chips perform under real workloads. You'll spend mornings digging into benchmark results - figuring out where cycles are being lost

Sr. SoC Technical Program Manager, Silicon and System Group - Hardware Bengaluru, Karnataka, IND As a Senior SoC Technical Program Manager, you will orchestrate the pre-silicon readiness, silicon bring-up, and validation phases for next-generation SOC solutions in Amazon Devices. You will interface with cross-functional engineering teams spanning RTL, verification, bare metal software, firmware, validation, and hardware to ensure successful first silicon boot and production readiness. Key job responsibilities * Collaborate with SOC architecture, RTL design, and physical design teams to ensure backend readiness and pre-silicon software readiness including bare metal software, boot ROM, and early firmware on virtual platforms * Lead end-to-end silicon bring-up from first silicon arrival through successful boot and functional validation, coordinating bare metal software development and IP configuration validation * Drive Silicon Validation (SV) and Electrical Validation (EV) activities including comprehensive test plans, electrical characterization, and automated test framework development * Manage BSP development and integration including device drivers, bootloaders, and low-level firmware across all SOC IP blocks * Coordinate IP vendor-provided software components and drivers with internal BSP development, ensuring proper software abstraction layers and driver interfaces * Drive effective teamwork and collaboration across silicon design, verification, software, firmware, hardware, and validation teams with competing priorities * Conduct weekly bring-up status reviews, manage project status and risk reviews from tape-out through production release * Define and track key bring-up performance metrics including time-to-boot, validation coverage, and issue resolution velocity * Work with external silicon vendors, IP providers, and validation partners to coordinate bring-up activities and

Senior Silicon Validation Engineer, Volume Production and Yield New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. We are seeking a highly motivated and experienced Silicon Engineer to drive our Volume Production and Yield efforts. In this pivotal role, you will be the primary technical owner for the transition of our silicon designs into high-volume factory manufacturing, delivering screening packages to factory partners and driving continuous silicon yield monitoring, failure analysis, voltage margin characterization, and improvement across the product lifecycle. You will leverage AI-driven data analytics and machine learning techniques to optimize yield, accelerate failure debug, and enhance overall silicon quality. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Provide technical guidance and expertise for volume productization and post-silicon yield enhancement. Define and deliver silicon screening packages to factory organizations. Execute and refine the silicon yield management strategy, leading failure analysis, root cause debug of limiters, and production data analysis. Leverage AI/ML tools

AI/ML Silicon Validation Lead, Google Cloud, TPU Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The Platform Enablement team is responsible for the development, bring-up and qualification, deployment, sustaining the quality of our AI/ML custom silicon. We plan and integrate hardware and software stacks and operate them on emulation, simulation and post-silicon platforms. We work closely with silicon design, platform hardware, firmware and software teams to enable on-time delivery of high quality silicon products. As a Manager, you will be responsible for growing the team through hiring, developing a psychologically safe environment for the team to succeed, enabling people development through effective career conversations, mentoring and building a strong community. In this role, you will be working on building, managing and leading a team of engineers responsible for post-silicon validation of AI/ML SoC which uses technology, working closely with the architecture, design, verification, firmware, software and platform leads, ensure timely silicon bring-up, enablement and debug closures and driving the preparation of necessary tests and collaterals for effective

Silicon Reliability Engineer Shanghai (JingAn) posted: Posted Today

Principal Full Stack Developer Additional Posting Location(s) US-CA-San Jose|US-CA-Silicon Valley|US-CA-Sunnyvale|US-CA-Mountain View|US-CA-Santa Clara Additional Location(s): Additional Posting Location(s) US-CA-San Jose|US-CA-Silicon Valley|US-CA-Sunnyvale|US-CA-Mountain View|US-CA-Santa Clara Diversity - Innovation - Caring - Global Collaboration - Winning Spirit - High Performance At Boston Scientific, we'll give you the opportunity to harness all that's within you by working in teams of diverse and high-performing employees, tackling some of the most important health industry challenges. With access to the latest tools, information and training, we'll help you in advancing your skills and career. Here, you'll be supported in progressing - whatever your ambitions. About the role: Boston Scientific was recognized as a Glassdoor Best Place to Work in 2026, ranking No. 15 on the Top 100 list, reflecting the culture our employees experience every day. The Principal Full Stack Developer serves as a senior technical leader responsible for shaping the design and delivery of innovative digital platforms that improve patient outcomes, connect medical devices, and enhance clinician experiences worldwide. This role architects and delivers enterprise-grade applications across the full stack, from intuitive front-end interfaces to scalable, secure back-end systems and cloud-native microservices. The position plays a critical role in advancing high-performing, compliant digital health and device software solutions while fostering engineering excellence and cross-functional collaboration. At Boston Scientific, we value collaboration an

SoC Input Output Architect, Silicon, Google Cloud Tel Aviv, Israel; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Google's Silicon team is driving the future of cloud data center computing. As a System on Chip Input Output (SoC IO) Architect, you will help define a new generation of Google's products. You will have pivotal responsibilities and serve as the organization Mobile Industry Processor Interface (MIPI) focal point. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of

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ML Kernel Performance Engineer, Edge AI and Science Vancouver, British Columbia, CAN Amazon Devices is an inventive research and development company that designs and engineers high-profile consumer products like the Kindle family, Fire Tablets, Fire TV, Health & Wellness devices, Amazon Echo, and Astro. We are building the next generation of edge AI capabilities through our advanced compression platform and custom neural accelerator silicon. Within Edge AI & Science, the AI Platform team builds a compression platform-the first of its kind-enabling 20-100x neural network compression for edge and cloud deployment. As model sizes grow from billions to hundreds of billions of parameters, compute efficiency becomes the single largest return on engineering investment during training. The gap between eager-mode Python and optimized GPU execution is where months of training time are won or lost. We are looking for an ML Kernel Performance Engineer to work at the hardware-software boundary of this platform, crafting high-performance CUDA and Triton kernels that make our compression algorithms run at peak efficiency during training, fine-tuning, and inference. You will build the tooling and kernel libraries that democratize GPU performance optimization across the team, enabling scientists and engineers to profile, diagnose, and fix kernel bottlenecks without needing to be CUDA experts themselves. Working alongside compression scientists and platform engineers, you will ensure that novel quantization schemes (ternary, nonary, mixed-precision) and sparse computation patterns translate into real throughput gains on GPU hardware. Your work will directly accelerate every training run in the organization and unlock deployment of compressed