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  • Hardware Interface Project Lead (Teradyne, San Jose, CA)

    Teradyne - San Jose, CA
    Indexed from Successfactors Benefit evidence checked May 7, 2026 Comp disclosed in posting
    posted 109 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Operations From the posting source - Senior From the posting source Inferred from posting Verified parental leave: 4 wk Inferred from posting Verified non-birth-parent leave: 4 wk $135K-$135K From the posting source Inferred from posting Childcare support Equity

    Hardware Interface Project Lead (Teradyne, San Jose, CA) San Jose, CA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and drives excellence in every connection. We are fueled by creativity and diversity of thought in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion that respects individual strengths, perspectives, and experiences-because better teams deliver better outcomes. Opportunity Overview As a HW Interface Project Coordinator, you will lead the execution of hardware interface development programs supporting advanced ATE systems. This role owns end-to-end project delivery-ensuring designs meet performance, quality, cost, and schedule targets-while coordinating across engineering, suppliers, and operations. Lead planning an

  • UI Designer (Design System)

    DexCom - Vilnius, Lithuania
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 110 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    UI Designer (Design System) Vilnius, Lithuania posted: Posted Yesterday

  • Software Engineer Intern, Implant

    Neuralink - Austin, Texas, United States; South San Francisco, California, United States
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 509 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Entry From the posting source Salary not disclosed From the posting source Equity Inferred from posting 401(k) reported

    Software Engineer Intern, Implant Austin, Texas, United States; South San Francisco, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Software Team is responsible for the end to end software stack that manages implant communication, verification, manufacturing and monitoring. We own client side SDKs and full-stack platforms that are used by various divisions within the company. We are looking for versatile engineers who are interested in architecting and implementing elegant software solutions and who thrive with the autonomy to propose creative approaches to problems. Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us. Job Responsibilities: As a Software Engineer Intern on the Brain Interfaces Software Team, your responsibilities will encompass: - Developing and improving Neuralink's Implant and Charger SDK - Maintaining Neuralink's brain interface software and firmware build tooling - Developing and improving Neuralink's Implant manufacturing line acceptance

  • Intel Process Integration Engineer - (BE)

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 112 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Intel Process Integration Engineer - (BE) 2 Locations posted: Posted 3 Days Ago

  • Staff Software Applications Engineer

    Maxlinear Inc - San Jose, CA, US
    Indexed from Icims Comp disclosed in posting
    posted 111 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Staff Plus From the posting source $115K-$170K From the posting source Equity

    Staff Software Applications Engineer San Jose, CA, US Responsibilities MaxLinear is seeking a Staff Software Applications Engineer to join our team. In this role, you will focus on the following: Work with local customers and support their product designs with components from MaxLinear's Data Center Connectivity division on the following products: high-speed PAM4 DSPs and Transimpedance Amplifies (TIAs), used in IMDD optical modules, Linear Receive Optics (LRO) modules, Active Electrical Cables (AECs), electrical retimers and similar products requiring high-speed SERDES interfaces Support MaxLinear DSP integration into customer products Address customer technical questions beyond software Write and support example microcontroller code to interface with MaxLinear DSP APIs Collaborate on GUI definition and/or development Develop conference and customer demonstrations of MaxLinear DSP capabilities Optimize SERDES and optical links through DSP signal processing block configuration Some travel around California and occasionally Asia Qualifications Proficient in programming languages C, C++, and Python Knowledge of latest OIF's Common Management Interface Specification (CMIS) Experience programming microcontrollers such as STMicroelectronics STM32 series Knowledge of I2C and SPI interfaces and developing drivers Experience with optimizing PAM4 signals for receiving and transmitting Experience with configuring and coding for RTOS, GUI development, and signal processing experience preferred Experience working with lab equipment such as

  • Analog and Mixed-Signal IC Design Engineer Intern

    Neuralink - South San Francisco, California, United States
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 222 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Entry From the posting source Salary not disclosed From the posting source Equity Inferred from posting 401(k) reported

    Analog and Mixed-Signal IC Design Engineer Intern South San Francisco, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. To accelerate our pathway to human ready brain-computer interfaces, you will have the opportunity to partner with our electrical, microfabrication, chip designers, neuro and mechanical engineers. Job Responsibilities: We are looking for Analog and Mixed-Signal IC Design Engineer Interns who are interested in architecting and implementing innovative solutions with high energy-efficiency and compact silicon footprint and who thrive with the autonomy to propose creative approaches to problems. Neuralink strives to be, as much as possible, a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals with different skill sets and perspectives, and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all

  • Java with AI Engineering - Assistant Vice President

    Citigroup Inc. - PUNE, Mahārāshtra, India
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Java with AI Engineering - Assistant Vice President PUNE, Mahārāshtra, India

  • Software Engineer, Implant

    Neuralink - Austin, Texas, United States; South San Francisco, California, United States
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 509 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source $119K-$200K From the posting source Equity Inferred from posting 401(k) reported

    Software Engineer, Implant Austin, Texas, United States; South San Francisco, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Software Team is responsible for the end to end software stack that manages implant communication, verification, manufacturing and monitoring. We own client side SDKs and full-stack platforms that are used by various divisions within the company. We are looking for versatile engineers who are interested in architecting and implementing elegant software solutions and who thrive with the autonomy to propose creative approaches to problems. Neuralink strives to be a meritocratic environment: we require honest and transparent communication to ensure the best ideas win out, and we believe the best solutions emerge and the best teams are created when you assemble high-performing individuals and allow them to engage in rigorous and thoughtful inquiry. We want to work with exceptional people, and, to the extent that you excel, we want you to take on more responsibility and help all of us succeed. If this speaks to you, come join us. Job Responsibilities: As a Software Engineer on the Brain Interfaces Software Team, your responsibilities will encompass: - Developing and improving Neuralink's Implant and Charger SDK - Maintaining Neuralink's brain interface software and firmware build tooling - Developing and improving Neuralink's Implant manufacturing line acceptance software -

  • Principal Systems Engineering Architect

    Maxlinear Inc - San Jose, CA, US
    Indexed from Icims Comp disclosed in posting
    posted 111 days ago

    Why we showed this

    Description: "interface"
    Unspecified Teaching Education From the posting source - Principal From the posting source $164K-$215K From the posting source Equity

    Principal Systems Engineering Architect San Jose, CA, US Responsibilities MaxLinear is seeking a Principal Systems Engineering Architect to join our Analog Mixed Signal (AMS) group. The AMS team develops a broad portfolio of integrated solutions spanning high speed and embedded connectivity interfaces (bridges, serial transceivers, isolators) and power management, supporting data center, industrial, and embedded platforms. In this role, you will focus on the following: Drive end-to-end systems definition across silicon architecture, firmware, software drivers, and hardware integration, working closely with design, applications, product management, and customers to deliver differentiated, production ready solutions Define and own systems level architecture for connectivity and interface products, including USB based connectivity, PCIe based interfaces, and serial and control protocols (UART, I²C, SPI, GPIO, and related interfaces) Lead architectural decisions across protocol partitioning and system integration, performance, latency, power, and scalability trade offs, and register maps, configurability, and extensibility Partner with Product Management on product definition, roadmap planning, competitive and system level differentiation Engage directly with customers to capture system level requirements and support complex technical discussions and escalations Drive cross functional alignment across analog, digital, firmware, software, package, test, and applications teams Own system requirements, architecture documents, and design r

  • Software Engineer, Next Gen

    Neuralink - South San Francisco, California, United States
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 432 days ago

    Why we showed this

    Description: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source $151K-$281K From the posting source Equity Inferred from posting 401(k) reported

    Software Engineer, Next Gen South San Francisco, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Next Gen team at Neuralink is developing the next generation of brain-computer interfaces. We are laying the groundwork for intuitive, high-dimensional, and bidirectional interfaces between brains and machines, with the goal of helping people challenged by a variety of neurological disorders and conditions. Our team consists of scientists and engineers, working closely together to define the engineering requirements for these future products. Job Description and Responsibilities: As a Software Engineer, you will write, test and deploy software that interacts with our neural interfaces and other data acquisition systems to decode and modulate brain activity. We are looking for hands-on engineers who are excited to own the end-to-end engineering of next-generation software systems for the control of neural stimulation, visual prosthesis (Blindsight) and medical imaging data pipelines. Successful candidates will be highly adaptable, able to deploy their core technical and creative skills to tackle a wide range of problems, and have a keen sense of urgency. The job responsibilities will include: - Developing, validating, testing, and deploying software systems - Writing algorithms to decode and modulate neural activity - Designing user experiences centered around neural control of devices - Mentoring others in achieving engineering excellence through code review, design review,

  • Multimodal

    Microsoft - US
    Indexed from Microsoft Custom Benefit evidence checked Jun 13, 2026
    posted 294 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Multimodal US

  • UI designer

    Autodesk - Tel Aviv, ISR
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 140 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    UI designer Tel Aviv, ISR posted: Posted 30+ Days Ago

  • Research Engineer - Brain Computer Interface Models

    Zyphra - San Francisco, California, United States
    Indexed from Ashby
    posted 196 days ago

    Why we showed this

    Description: "interface"Title: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Inferred from posting Unlimited PTO

    Research Engineer - Brain Computer Interface Models San Francisco, California, United States Zyphra is an artificial intelligence company based in San Francisco, California. The Role: As a Research Engineer - Brain Computer Interface Models , you will be a core contributor to Zyphra's BCI work, building the next generation of open-source EEG and brain-computer interface models. You will be involved across the full model lifecycle, from data collection and preprocessing to designing novel architectures and training methodologies. You'll Work Across: - Large-scale EEG model training runs and evaluation - Architecture and training methodology ablations and innovations - Dataset collection and preprocessing for EEG and other BCI modalities - Performance optimization of the training stack - Integration of models into real-world BCI applications What We're Looking For / Requirements: - Organized, methodical researcher who can take ownership of a project component, communicate their process clearly, and deliver a working module - Excellent communication and collaboration skills, with clean and concise coding practices - Strong implementation and prototyping skills, with comfort working across both research and engineering at scale - Ability to learn new domains quickly, orient oneself in the academic literature, and implement new ideas, creatively borrowing concepts from other modalities and applying them to EEG domain - Interest in neural data such as EEG, MEG, fMRI as well as building foundation models in a much less explored space - Proficiency with PyTorch and Python Qualifications / Additional Skills: - Experience with VAEs, GANs, diffusion models, and contrastive learning - Familiarity

  • Junior Layout Engineer

    NXP Semiconductors - Catania
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 140 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Junior Layout Engineer Catania posted: Posted 30+ Days Ago

  • Intern Assembly Engineering

    STMicroelectronics - Muar, Malaysia
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Entry From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Intern Assembly Engineering Muar, Malaysia

  • Sr. Project Engineer

    Coherent Corp. - Monroe, CT, United States
    Indexed from Oracle Recruiting Cloud Benefit evidence checked Jun 13, 2026
    posted 169 days ago
    Unspecified Engineering From the posting source - Senior From the posting source Salary not disclosed Inferred from posting Childcare support Equity Inferred from posting 401(k) reported

    Sr. Project Engineer Monroe, CT, United States Job Summary: Project Engineer is responsible for leading and managing engineering projects from conception through completion, ensuring that all aspects are executed on time, within scope, and within budget. Activities include planning, quoting, tracking, reporting, interfacing with suppliers, determining capital equipment needs, interfacing with customers, and interfacing with other teams within Coherent (both in CT and at other locations). Following the expertise of the Monroe CT site, the majority of projects will be focused on advanced materials (ceramics, metal matrix composites, coating, etc.), advanced machining (multi-axis milling, grinding, laser, EDM, ultrasonic, lapping, polishing), and advanced metrology (CMM, optical, interferometry). Successful new products will be transferred to manufacturing (specifying equipment, training personnel, monitoring results). Position includes participation in Lean, Six-sigma, Kaizen, FMEA, 6S, and yield enhancement activities.

  • Desktop Support Engineer

    Ouster Inc - Location not specified
    Indexed from Jazzhr Benefit evidence checked Jun 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Desktop Support Engineer Desktop Support Engineer

  • Senior Computer Scientist

    Adobe Inc. - Noida
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 16 wksource Resolvable source Verified non-birth-parent leave: 16 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Computer Scientist Noida posted: Posted Today

  • Head of Data

    Overwolf - Overwolf's lair
    Indexed from Custom Structured
    posted 111 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Salary not disclosed

    Head of Data Overwolf's lair Head of Data

  • Maintenance Team Leader

    Interface Inc - LaGrange, GA
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 124 days ago

    Why we showed this

    Employer: "interface"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Maintenance Team Leader LaGrange, GA posted: Posted 15 Days Ago

  • UI/UX Engineer

    Leidos - San Diego, CA
    Indexed from Workday Benefit evidence checked May 7, 2026
    posted 133 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reported

    UI/UX Engineer San Diego, CA posted: Posted 24 Days Ago

  • UI/UX Designer

    CACI - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    UI/UX Designer 2 Locations posted: Posted Today

  • Mechanic I (3rd shift)

    Interface Inc - LaGrange, GA
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 131 days ago

    Why we showed this

    Employer: "interface"
    Unspecified Trades From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Mechanic I (3rd shift) LaGrange, GA posted: Posted 22 Days Ago

  • API Team Leader

    Vodafone Group - Irakleio - Crete, Greece
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 109 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    API Team Leader Irakleio - Crete, Greece

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