Intel jobs

Chief of Staff to the Managing Director – Intel Customer Support 2 Locations posted: Posted 9 Days Ago

CoDesign & NextGen - New College Grad Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role Engineers in the CoDesign and NextGen organization work at the interface of software and hardware helping everything from high performance kernel design, next generation ASIC performance modeling and tuning, new system bringup and software tuning, system robustness and simulations. As an new engineer you'll be expected to learn the Cerebras products and platforms end to end starting at the base layer of programming the Wafer Scale Engine through kernel development, modeling performance for our software products and validating the work

System Debug Engineer Country Taiwan | City Bade Job Req ID: 27426 Job Summary: We are looking for a Sr. System Debug Engineer to debug and to support customer and other internal deparmtnets for solving puter system issues. In this role, you will work with other departments and provide solutions for the issues and product quality improvement. The ideal candidate should be familiar with Intel low level debugging. Experience using Intel Target Probe (ITP) tool is a plus. Essential Duties and Responsibilities: Diagnose the root cause of server system failures and isolate the components/failure nodes Interface with RD, System teams, and customer support to improve Supermicro products quality in early DVT/PVT stage Develop and publish test reports and communicate findings to other team members Using software to improve testing techniques / procedures for analyzing system failure data efficiently Support product technology know-how & troubleshooting skills transfer to Production from PVT to MP stage Qualifications: Bachelor of Science in Electrical Engineering with minimum 3 years of working experience preferred Proficient in Linux and Windows OS Lab and debug skills are required, including experience working with and analyzing output from test equipment such as digital multi-meter and oscilloscopes, along with soldering and debugging skills Strong problem-solving capability Familiar with Intel ITP/DCI and Intel CPUs & Chipset architecture or AMD CPU/GPU & Chipset architecture is a plus EEO Statement Supermicro is an Equal Opport

Senior Clock Architecture & Design Engineer 2 Locations posted: Posted 30+ Days Ago

Senior System Debug Engineer Country Taiwan | City Bade Job Req ID: 27425 Job Summary: We are looking for a Sr. System Debug Engineer to debug and to support customer and other internal deparmtnets for solving puter system issues. In this role, you will work with other departments and provide solutions for the issues and product quality improvement. The ideal candidate should be familiar with Intel low level debugging. Experience using Intel Target Probe (ITP) tool is a plus. Essential Duties and Responsibilities: Diagnose the root cause of server system failures and isolate the components/failure nodes Interface with RD, System teams, and customer support to improve Supermicro products quality in early DVT/PVT stage Develop and publish test reports and communicate findings to other team members Using software to improve testing techniques / procedures for analyzing system failure data efficiently Support product technology know-how & troubleshooting skills transfer to Production from PVT to MP stage Qualifications: Bachelor of Science in Electrical Engineering with minimum 7 years of working experience preferred Proficient in Linux and Windows OS Lab and debug skills are required, including experience working with and analyzing output from test equipment such as digital multi-meter and oscilloscopes, along with soldering and debugging skills Strong problem-solving capability Familiar with Intel ITP/DCI and Intel CPUs & Chipset architecture or AMD CPU/GPU & Chipset architecture is a plus EEO Statement Supermicro is an Equal Opport

Machine Learning Compute Efficiency Lead, Infrastructure & Planning Cupertino, United States of America Apple's Platform Acceleration & Compute Efficiency (PACE) is a high-leverage team operating at the critical intersection of our ML organizations, underlying compute infrastructure, and core platform tooling. Our mission is to empower Apple's software engineering teams with efficient, scalable compute. By driving out operational friction and optimizing the broader machine learning ecosystem, we directly accelerate the pace of development across the company. As foundation models become increasingly central to Apple's user experiences, maximizing the efficiency of our ML compute is paramount. In this role, you will focus relentlessly on compute efficiency, ensuring that Apple's models run as fast, reliably, and cost-effectively as possible. You will tackle massive optimization challenges, from maximizing hardware utilization across GPUs, TPUs, and custom Apple Silicon, to shaping workload scheduling and capacity allocation for large model serving. We are seeking a Senior Architect with deep expertise in ML infrastructure to act as a linchpin for Apple's foundational inference strategy. You will be instrumental in defining, establishing, and monitoring compute efficiency metrics across the software engineering organization. By partnering closely with model developers and infrastructure providers, your work will directly reduce serving costs, shape core engineering decisions, and enable the highly efficient, scalable inference required to power Apple Intelligence for hundreds of millions of users. - Own and support ML compute management for Apple's inference workloads (GPU, TPU, and custom silicon) to enable large-scale model serving. - Collaborate closely with Apple Intelligence and ML

Intel and Ops Integrator (PSYOP Support) USA NE Offutt AFB posted: Posted 11 Days Ago

Intel Analyst - Foreign Ownership Control Influence Aberdeen Proving Ground, MD, US posted: Posted 7 Days Ago

Senior Performance Engineer, Inference Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role We are hiring a Senior Performance Engineer to join our Product team. You are an expert on state-of-the-art inference performance and will serve as our resident expert on how Cerebras stacks up against alternative inference providers on both price and performance. This role sits at the intersection of performance benchmarking from first principles and competitive intelligence. The role has two core pillars: - Performance Benchmarking You will build, run, and maintain reproducible benchmarks that measure Cerebras inference performance for real customer workloads. This

IP Logic Design Engineer Malaysia, Penang posted: Posted 18 Days Ago

National Security Solutions (NSS) Internship – INTEL DE/MBSE Intern King of Prussia, Pennsylvania posted: Posted 30+ Days Ago

Intel Analyst – Group 1-3 Technical Analyst Aberdeen Proving Ground, MD, US posted: Posted 7 Days Ago

CPU Microarchitect/RTL Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer who can drive CPU multi-level cache subsystem architecture and RTL development for multi-processor systems. As a CPU Microarchitect/RTL Engineer, you will participate in the following: • Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification • RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for formal verification • Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance • Design delivery - work

Principal Business Intell. Analyst, Power BI Milwaukee-Wisconsin-United States of America posted: Posted 4 Days Ago

Senior CPU Performance Architect Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan and evaluate ARM's architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and microarchitecture studies. Lead collaboration with design and verification teams to develop efficient CPU implementation. Define and write CPU subsystem architecture specifications. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer

Lead Data Scientist- Comp Intel Tower 02, Manyata Embassy Business Park, Racenahali & Nagawara Villages. Outer Ring Rd, Bangalore 540065 posted: Posted 28 Days Ago

Accountant India, Bangalore posted: Posted 30+ Days Ago

Account Executive Virtual US posted: Posted Today

Principal Engineer: XeSS and Neural Graphics US, Oregon, Hillsboro posted: Posted 30+ Days Ago

Senior Accountant Malaysia, Penang posted: Posted Yesterday

Senior CPU Performance Architect 3 Locations posted: Posted 9 Days Ago

Principal Engineer - FPGA US-NY-SKANEATELES-721 VISIONS DRIVE posted: Posted 30+ Days Ago

College Graduate 2 Locations posted: Posted 30+ Days Ago

Analog Engineer India, Bangalore posted: Posted 17 Days Ago