NXP Semiconductors jobs
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Hardware Integration Engineer
Base Power - Austin, TX, Austin, Texas, United StatesIndexed from Ashbyposted 341 days agoWhy we showed this
Role: semantic matchHardware Integration Engineer Austin, TX, Austin, Texas, United States About Base Base is America's next-generation power company. We're rebuilding the foundation of modern civilization-electricity-by deploying a vast network of distributed batteries that is transforming today's fragile, centralized grid into a resilient and abundant system. We are engineers, operators, and creatives solving some of the most complex, interdisciplinary challenges of our time. About the Role We are looking for a Hardware Integration Engineer to help design and integrate the next generation of Base Power's residential battery storage, inverter, and microgrid interconnect device (MID) systems. This role requires strong electrical engineering fundamentals and hands-on experience with complex energy storage hardware. You'll play a critical role in building safe, reliable, and scalable hardware systems that power homes and communities. What You'll Do - Design and integrate battery management systems (BMS), inverters, and MID hardware for residential energy applications. - Develop and maintain system architecture and electrical schematics for multi-component energy systems. - Conduct testing, validation, and troubleshooting of integrated hardware systems. - Partner with software teams to ensure seamless hardware/software integration and control algorithm development. - Support regulatory compliance and product certification processes to meet industry standards. What You'll Bring - BS/MS in Electrical Engineering (or related field) with 3+ years of hardware development experience, ideally in energy storage or power systems. - Core Technical Knowledge : - Electrical engineering fundamentals: circuit analysis, analog/digital electronics, high-voltage design. - Power electronics: DC-DC/DC-AC converters, inverters, switching power supplies, grid-tie systems. - Battery systems: Li-ion/LiFePO4 technologies,
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Coherent NoC IP Design Engineer
Google - Bengaluru, Karnataka, IndiaIndexed from Google Custom Benefit evidence checked May 7, 2026posted 75 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedCoherent NoC IP Design Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Own and execute the Register-Transfer Level (RTL) design and micro-architecture for high-performance fabrics and Network on Chip (NoC) subsystems from concept to tape-out. Run and analyze Power Performance Area (PPA) for the designs, and do design trade-offs to understand/optimize the design. Perform in-depth search performance analysis of NoC topologies, including latency modeling, bandwidth bottleneck identification, and arbitration tuning. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Drive front-end implementation tasks,
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IT Systems Engineer - DevOps LDAP Services
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 104 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIT Systems Engineer - DevOps LDAP Services 2 Locations posted: Posted 30+ Days Ago
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Senior VLSI Engineer
NVIDIA Corporation - 2 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 73 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior VLSI Engineer 2 Locations posted: Posted Today
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ASIC Design Engineer, Clocks
NVIDIA Corporation - China, ShanghaiIndexed from Workday Benefit evidence checked Jun 13, 2026posted 89 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedASIC Design Engineer, Clocks China, Shanghai posted: Posted 16 Days Ago
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Applications / Software Engineer in Roznov or Ostrava
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 89 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedApplications / Software Engineer in Roznov or Ostrava 2 Locations posted: Posted 16 Days Ago
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ASIC Emulation Engineer / Technical Leader
ThousandEyes - Bangalore, IndiaIndexed from Phenom Peopleposted 129 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Senior From the posting source Salary not disclosedASIC Emulation Engineer / Technical Leader Bangalore, India Join our team as a Senior ASIC Emulation Engineer and lead the development of advanced emulation environments for cutting-edge networking ASICs. Collaborate with top-tier teams, drive innovation in performance testing, and play a key role in verifying multi-terabit systems. Shape the future of semiconductor technology with us!
- posted 131 days ago
Why we showed this
Role: semantic matchUnspecified Engineering From the posting source - Entry From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedHardware Engineer Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities: - Mainly focus for system schematic review and mechanical stacking review with mechanical engineers and PCB layout review with layout engineers. - Work with RF engineers to figure out performance issues of radios. - Review design derating and suggest design update due to DFM (design for manufacturing), DFA(design for assembly) and DFC (Design For Cost.) - Schematic and BOM maintain and review. - Write test plans for testing coverage, executes tests, and documents test results for projects. - Report projects' status and issue tracking to internal. - Teardown and review new products in the market. Qualifications: - BS or MS in EE engineering. - Junior/New grads are welcome. - Leadership in a project. - Good working knowledge of system level architecture and RF fundamentals. - Basic knowledge of EE lab equipment including: oscilloscopes, multimeters, power supplies, etc. - Good understanding of RF metrics. - Proficiency on PCB and
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Senior Engineer - NAND CMOS Device
Micron Technology, Inc. - Fab 10N/X, SingaporeIndexed from Workday Benefit evidence checked Jun 7, 2026posted 104 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Engineer - NAND CMOS Device Fab 10N/X, Singapore posted: Posted 30+ Days Ago
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Intern (f/m/d) Corporate Real Estate & Workplace
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 104 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Finance From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIntern (f/m/d) Corporate Real Estate & Workplace Hamburg posted: Posted 30+ Days Ago
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Principal Engineer, Analog Mixed-Signal IC Layout
Astera Labs - Bengaluru, Karnataka, IndiaIndexed from Greenhouse Benefit evidence checked Jun 7, 2026posted 167 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Staff Plus From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Engineer, Analog Mixed-Signal IC Layout Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who
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Chip Design Engineer
NVIDIA Corporation - Israel, Tel AvivIndexed from Workday Benefit evidence checked Jun 13, 2026posted 104 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedChip Design Engineer Israel, Tel Aviv posted: Posted 30+ Days Ago
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Edge AI Model Optimization Software Engineer
NXP Semiconductors - GuadalajaraIndexed from Workday Benefit evidence checked May 7, 2026posted 104 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedEdge AI Model Optimization Software Engineer Guadalajara posted: Posted 30+ Days Ago
- posted 75 days ago
Why we showed this
Role: semantic matchSenior EE Hardware Engineer Shenzhen, 44, CN Position Description At a Glance Legrand has an exciting opportunity for a Senior EE Hardware Engineer to join the Audio Video Division in Shenzhen China. As a Legrand AVD Engineer, will be responsible for designing, testing and verifying a select lineup of complex USB/AV/Cable products. You will also create supporting design files and test report documentation necessary for communicating results and maintaining long-term record reliability. What Will You Do? Major Duties and Responsibilities: · Provide (USB/AV/Cable/Cloud-connected) System and circuit-level Hardware EE engineering design support - Mobility signal conversion and extension products - Active device single output conversion dongles (Example: USB Type C to HDMI or DisplayPort, HDBase-T Extenders) - Active device multiple output conversion dongles (Example: USB Type C to VGA + HDMI + Ethernet + Power) - Active Copper or Active Optical Cables - Laptop/Tablet Docking Station products - Active device multiple input + multiple outputs - Passive Cables (USB, HDMI, DisplayPort, Category) - Cloud-connected Systems (Example: Remote AV Switch control/monitoring via cloud platforms) · Provide (USB/AV/Cable/Cloud-connected) Design Validation and Functional/Compatibility Test (hardware/firmware/software/mechanical) - To ensure quality of products in terms of compatibility to C2G and other 3rd party products and conformance to recognized industry standards · Provide appropriate production support - Transfer product from protot
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Analog Layout Engineer
Apple - Austin, United States of AmericaIndexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in postingposted 82 days agoWhy we showed this
Role: semantic matchUnspecified Engineering From the posting source - Mid From the posting source $155K-$275K From the posting source Equity Inferred from posting 401(k) reportedAnalog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC
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Senior Chip Design Engineer
NVIDIA Corporation - Israel, Tel AvivIndexed from Workday Benefit evidence checked Jun 13, 2026posted 104 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Chip Design Engineer Israel, Tel Aviv posted: Posted 30+ Days Ago
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Sr. Principal Field Application Engineer – Robotics
NXP Semiconductors - BeijingIndexed from Workday Benefit evidence checked May 7, 2026posted 77 days agoWhy we showed this
Employer: "nxp"Employer: "semiconductors"Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr. Principal Field Application Engineer – Robotics Beijing posted: Posted 4 Days Ago
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Senior Chip Design Verification Engineer
NVIDIA Corporation - 2 LocationsIndexed from Workday Benefit evidence checked Jun 13, 2026posted 97 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Chip Design Verification Engineer 2 Locations posted: Posted 24 Days Ago
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Interconnect Hardware Engineer - Networking
NVIDIA Corporation - Denmark, RoskildeIndexed from Workday Benefit evidence checked Jun 13, 2026posted 103 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedInterconnect Hardware Engineer - Networking Denmark, Roskilde posted: Posted 30 Days Ago
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Senior Hardware Engineer
Eaton Corporation - Shenzhen, Guangdong, CHN, 518101Indexed from Eightfold Benefit evidence checked Jun 13, 2026posted 72 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Hardware Engineer Shenzhen, Guangdong, CHN, 518101
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Embedded SW Developer with Rust - Security
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 104 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedEmbedded SW Developer with Rust - Security 2 Locations posted: Posted 30+ Days Ago
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Hardware Electrical Engineer, Augmented Reality Glasses
Google - San Jose, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 80 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $132K-$190K From the posting source Equity Inferred from posting 401(k) reportedHardware Electrical Engineer, Augmented Reality Glasses San Jose, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Hardware Engineer on the Google Android XR Hardware team, you will design, implement, and deliver Next Generation hardware systems and AR glasses. You will drive hardware solutions from concepts through production, ensuring robust designs that meet performance, efficiency, reliability and ability to scale. Your work will directly impact how users perceive the power of Android XR and apps/services including Gemini. For decades, the computing revolution has reshaped our world driven by breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap - the convergence of AI and XR. This is more than just new devices - it's about reimagining how we interact with the world around us. We're building a future where lightweight XR devices like smart glasses and headsets pair with helpful AI to augment human intelligence, offering personalized, conversational, and contextually aware experiences. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $132000 - $190000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Gather system requirements for product management and cross functional
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Senior Engineer Analog Layout
Infineon Technologies - Penang (Malaysia)Indexed from Eightfold Benefit evidence checked Jun 7, 2026posted 72 days agoWhy we showed this
Role: semantic matchUnspecified Data From the posting source - Senior From the posting source Salary not disclosed Inferred from posting 401(k) reportedSenior Engineer Analog Layout Penang (Malaysia)
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Facilities HVAC/Mechanical O&M Technician
NXP Semiconductors - Chandler (Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 104 days agoWhy we showed this
Employer: "semiconductors"Employer: "nxp"Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedFacilities HVAC/Mechanical O&M Technician Chandler (Office) posted: Posted 30+ Days Ago
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