Intel jobs

Identity Security - PKI Engineer 2 Locations posted: Posted 15 Days Ago

Senior Deep Learning Engineering - Autonomous Vehicles 2 Locations posted: Posted 29 Days Ago

NPI Process Integration Technician Malaysia, Penang posted: Posted 30+ Days Ago

CPU Implementation Methodology Engineer Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a member of the CPU implementation methodology team, you will help drive CPU design initiatives and flow development. This is a tremendous opportunity for an engineer with Synthesis and PNR experience to influence improvement for our design team. • Generate and validate new ideas, create flows and methodologies around them by working with CPU Designers, CAD teams and EDA tool vendors to improve PPA • Detailed analysis across partitions to understand optimization opportunities • Cross functional collaboration across STA, library, tech and post silicon teams to improve optimization during Implementation • Contribute to aspects of Synthesis and Physical Design Implementation methodologies Minimum Qualifications: Minimum BS and 3+ years of relevant industry experience Experience with implementing VLSI digital designs using SAPR tools with multi-GHz performance goals Experience with logic optimization trade-offs between area, timing and power Preferred Qualifications: Experience implementing

Semiconductor Device Modeling Engineer 2 Locations posted: Posted 30+ Days Ago

Silicon Packaging Design Engineer 2 Locations posted: Posted 23 Days Ago

Hardware Engineer (eInfochips) Bedford, Massachusetts, United States of America Embrace the opportunity to become a Hardware Engineer and drive innovation in semiconductor design. Work on cutting-edge hardware projects, from analog and mixed signal design to power supply systems. Collaborate with top engineers, leverage advanced tools, and contribute to next-generation technology. Shape the future of electronics with us in Bedford, MA!

Sr. Engineer, CPU RTL Design Austin, Texas, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You'll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. - Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. - Proficient in debugging RTL/logic across multiple design hierarchies and

Qubit Control IC Designer 2 Locations posted: Posted 9 Days Ago

GPU Design Engineer – Memory Hierarchy Santa Clara, United States of America Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day! modelers in order to assess the feasibility of ideas, refine ideas, and seed new ones. You will specify new micro-architecture and optimize existing ones; you will use your intuition gained from experience as a guide but not as a filter. The role requires the analysis of specific workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. As a member of the GPU micro-architecture team, you will collaborate to improve our processes and look for ways to boost the efficiency of the entire team! Minimum Qualifications: Experience with CPU or GPU architecture and micro-architecture concepts Experience in one of the following areas: cache, memory subsystem, on-chip interconnect network, data compression or GPU pipeline Minimum of BS degree and 10+ years of relevant experience Preferred Qualifications: Knowledge in C/C++ Experience in scripting languages such as Perl, Python and Ruby Proficiency in high performance, low power

Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles United States-Virginia-Dulles

Mechanical Project Engineer US, Arizona, Phoenix posted: Posted 11 Days Ago

SoC RTL Design Engineer India, Bangalore posted: Posted 28 Days Ago

Senior VLSI Integration Engineer 4 Locations posted: Posted 30+ Days Ago

Standard Cell Design Engineer Malaysia, Penang posted: Posted 30+ Days Ago

Manager - Data Center Asset tracking and Accounting Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role The Manager will be primarily responsible for tracking and recovery of Cerebras's data center infrastructure and assets globally through asset end of life. This leadership position requires an organized, highly motivated professional with the ability to drive operational and process improvements. The individual will perform a variety of tasks ranging from routine to complex analysis and play a critical part in asset tracking operations, including asset dispositions, transfers, and periodic cycle counts. This role requires comfort operating in a

Linux Driver Wifi developer Israel, Jerusalem posted: Posted 29 Days Ago

Manufacturing Linux Network Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role We are seeking an experienced Manufacturing Linux / Network Engineer to design, implement, and maintain robust IT and network infrastructure across our manufacturing facilities. The ideal candidate brings deep expertise in Linux systems administration (Red Hat / Rocky Linux), network security (Palo Alto firewalls), storage infrastructure, CI/CD pipelines (Jenkins), and infrastructure automation (Ansible). This role sits at the intersection of enterprise IT and plant-floor operations, and is critical to delivering the high availability, security, and performance that modern manufacturing environments demand. Responsibilities -

AI Frameworks Engineer - Intern PRC, Shanghai posted: Posted 30+ Days Ago

Analog Circuit Design Engineer India, Bangalore posted: Posted 30+ Days Ago

Chip Design Verification Engineer Israel, Tel Aviv posted: Posted 23 Days Ago

Member of Technical Staff (Software Engineer) Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras Systems Inc. has multiple openings for Member of Technical Staff (Software Engineer) Title : Member of Technical Staff (Software Engineer) Job Duties - Implement infrastructure to support high-performance, low-latency inference service. - Deploy and configure Kubernetes services to ensure scalability and reliability of inference workloads. - Optimize resource allocation and auto-scaling policies to handle variable inference demand while minimizing operational costs. - Integrate inference services with containerized environments using Docker and Kubernetes for orchestration. - Ensure high availability and fault tolerance by implementing

Field Applications Engineer - Robotics Virtual US posted: Posted 3 Days Ago

FSO Ireland Equipment Technicians Ireland, Leixlip posted: Posted 7 Days Ago