CPU Implementation Methodology Engineer
Apple - Austin, United States of America
Posted Apr 14, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
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- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
CPU Implementation Methodology Engineer Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a member of the CPU implementation methodology team, you will help drive CPU design initiatives and flow development. This is a tremendous opportunity for an engineer with Synthesis and PNR experience to influence improvement for our design team. • Generate and validate new ideas, create flows and methodologies around them by working with CPU Designers, CAD teams and EDA tool vendors to improve PPA • Detailed analysis across partitions to understand optimization opportunities • Cross functional collaboration across STA, library, tech and post silicon teams to improve optimization during Implementation • Contribute to aspects of Synthesis and Physical Design Implementation methodologies Minimum Qualifications: Minimum BS and 3+ years of relevant industry experience Experience with implementing VLSI digital designs using SAPR tools with multi-GHz performance goals Experience with logic optimization trade-offs between area, timing and power Preferred Qualifications: Experience implementing
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