Intel jobs

CUF TD Module Engineer Malaysia, Kulim posted: Posted 25 Days Ago

Senior STA Engineer, Sub-chip 3 Locations posted: Posted Yesterday

Design Verification Student Worker Mexico, Guadalajara posted: Posted 30+ Days Ago

Manufacturing Technical Supervisor (Operations) Malaysia, Penang posted: Posted 2 Days Ago

Senior Solutions Architect, Datacenter CPUs US, CA, Santa Clara posted: Posted 30+ Days Ago

Senior Thin Films Engineer 2 Locations posted: Posted 4 Days Ago

Retail Sales and Marketing Intern 2 Locations posted: Posted 14 Days Ago

Machine Learning Engineer, Platform Architecture Cupertino, United States of America At Apple, our Platform Architecture group is responsible for connecting our hardware and software into one unified system! You'll collaborate with engineers across Apple to design how our technologies work in unison, drive development of our renowned system-on-a-chip architecture and develop forward-looking prototype systems. Our team works at the intersection of ML applications and Apple silicon architecture. We collaborate with SoC/IP architecture, system, software, and algorithm teams to develop integrated, highly optimized solutions for machine learning applications. In this role, you will explore different ways of mapping ML workloads to Apple silicon and develop performance models/simulations. Your work will inform and validate architecture decisions. You will gain insights on how to make workloads run efficiently on our SoCs and communicate what we learn to software and algorithm teams. Create optimized implementations of ML workloads on Apple silicon including Neural Engine, GPU, and CPU. Collaborate with IP and SoC architecture teams to develop performance models and simulations of future hardware. Conduct performance studies to inform and validate architecture decisions. Collaborate with system teams to create high-level performance models of emerging ML techniques and analyze system architecture trade-offs. Minimum Qualifications: Bachelor's degree Ability to program in C/C++ and/or Python Knowledge of computer architecture fundamentals Domain knowledge in at least one hardware IP: ML HW accelerators or processing units such as GPU, image/video, CPUs, or similar Preferred Qualifications: MS or PhD in EE/CE/CS or related field, or 3+ years of relevant experience Experience

AI Software Development Engineer Romania, Timisoara posted: Posted 4 Days Ago

Linux Kernel Engineer US, Oregon, Hillsboro posted: Posted 30+ Days Ago

Senior CPU Design Verification Engineer, Emulation Austin, TX, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis. Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches. Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation. Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers. Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in both Design

Hardware Engineer - Level 5 United States-Colorado-Boulder

IO Design Architect – High Speed Memory Interfaces (m/f/d) Munich (MDC), Germany posted: Posted Today

Identity Security - PKI Engineer 2 Locations posted: Posted 15 Days Ago

Senior Deep Learning Engineering - Autonomous Vehicles 2 Locations posted: Posted 29 Days Ago

NPI Process Integration Technician Malaysia, Penang posted: Posted 30+ Days Ago

CPU Implementation Methodology Engineer Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! As a member of the CPU implementation methodology team, you will help drive CPU design initiatives and flow development. This is a tremendous opportunity for an engineer with Synthesis and PNR experience to influence improvement for our design team. • Generate and validate new ideas, create flows and methodologies around them by working with CPU Designers, CAD teams and EDA tool vendors to improve PPA • Detailed analysis across partitions to understand optimization opportunities • Cross functional collaboration across STA, library, tech and post silicon teams to improve optimization during Implementation • Contribute to aspects of Synthesis and Physical Design Implementation methodologies Minimum Qualifications: Minimum BS and 3+ years of relevant industry experience Experience with implementing VLSI digital designs using SAPR tools with multi-GHz performance goals Experience with logic optimization trade-offs between area, timing and power Preferred Qualifications: Experience implementing

Semiconductor Device Modeling Engineer 2 Locations posted: Posted 30+ Days Ago

Silicon Packaging Design Engineer 2 Locations posted: Posted 23 Days Ago

Hardware Engineer (eInfochips) Bedford, Massachusetts, United States of America Embrace the opportunity to become a Hardware Engineer and drive innovation in semiconductor design. Work on cutting-edge hardware projects, from analog and mixed signal design to power supply systems. Collaborate with top engineers, leverage advanced tools, and contribute to next-generation technology. Shape the future of electronics with us in Bedford, MA!

Sr. Engineer, CPU RTL Design Austin, Texas, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You'll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. - Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. - Proficient in debugging RTL/logic across multiple design hierarchies and

Qubit Control IC Designer 2 Locations posted: Posted 9 Days Ago

GPU Design Engineer – Memory Hierarchy Santa Clara, United States of America Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Join us to help deliver the next groundbreaking products containing an Apple designed GPU. As part of the GPU Memory Hierarchy Design team, you'll be responsible for crafting and building a GPU that enriches the lives of millions of people every day! modelers in order to assess the feasibility of ideas, refine ideas, and seed new ones. You will specify new micro-architecture and optimize existing ones; you will use your intuition gained from experience as a guide but not as a filter. The role requires the analysis of specific workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. As a member of the GPU micro-architecture team, you will collaborate to improve our processes and look for ways to boost the efficiency of the entire team! Minimum Qualifications: Experience with CPU or GPU architecture and micro-architecture concepts Experience in one of the following areas: cache, memory subsystem, on-chip interconnect network, data compression or GPU pipeline Minimum of BS degree and 10+ years of relevant experience Preferred Qualifications: Knowledge in C/C++ Experience in scripting languages such as Perl, Python and Ruby Proficiency in high performance, low power

Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles United States-Virginia-Dulles